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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td20 def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),
52 def: Pat<(int_hexagon_A2_addsat IntRegs:$src1, IntRegs:$src2),
56 def: Pat<(int_hexagon_A2_and IntRegs:$src1, IntRegs:$src2),
78 def: Pat<(int_hexagon_A2_max IntRegs:$src1, IntRegs:$src2),
82 def: Pat<(int_hexagon_A2_maxu IntRegs:$src1, IntRegs:$src2),
86 def: Pat<(int_hexagon_A2_min IntRegs:$src1, IntRegs:$src2),
90 def: Pat<(int_hexagon_A2_minu IntRegs:$src1, IntRegs:$src2),
100 def: Pat<(int_hexagon_A2_or IntRegs:$src1, IntRegs:$src2),
118 def: Pat<(int_hexagon_A2_sub IntRegs:$src1, IntRegs:$src2),
1997 def: Pat<(int_hexagon_V6_vand HvxVR:$src1, HvxVR:$src2),
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
13 (MI HvxVR:$src1, IntRegs:$src2)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
28 (MI HvxVR:$src1, HvxVR:$src2)>;
32 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
33 (MI HvxWR:$src1, HvxWR:$src2)>;
35 (MI HvxWR:$src1, HvxWR:$src2)>;
86 (MI HvxQR:$src1, HvxVR:$src2)>;
[all …]
H A DHexagonIntrinsicsV60.td119 (MI HvxWR:$src1, IntRegs:$src2)>;
127 (MI HvxVR:$src1, IntRegs:$src2)>;
131 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
132 (MI HvxWR:$src1, HvxVR:$src2)>;
135 (MI HvxWR:$src1, HvxVR:$src2)>;
139 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
143 (MI HvxWR:$src1, HvxWR:$src2)>;
147 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
151 (MI HvxVR:$src1, HvxVR:$src2)>;
163 def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrXOP.td174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
251 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
259 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
287 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
303 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrSSE.td28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
51 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
58 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
81 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
240 def : InstAlias<OpcodeStr#".s\t{$src2, $dst|$dst, $src2}",
5677 "vptest\t{$src2, $src1|$src1, $src2}",
5699 "ptest\t{$src2, $src1|$src1, $src2}",
5703 "ptest\t{$src2, $src1|$src1, $src2}",
[all …]
H A DX86InstrAMX.td93 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
97 "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
101 "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
105 "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
141 u8imm:$src2, u8imm:$src3),
143 timm:$src2, timm:$src3)]>;
145 u8imm:$src2, u8imm:$src3),
147 timm:$src2, timm:$src3)]>;
149 u8imm:$src2, u8imm:$src3),
153 u8imm:$src2, u8imm:$src3),
[all …]
H A DX86InstrFMA.td42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
83 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
184 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
192 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
205 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
397 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
404 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrShiftRotate.td35 "shl{b}\t{$src2, $dst|$dst, $src2}",
39 "shl{w}\t{$src2, $dst|$dst, $src2}",
43 "shl{l}\t{$src2, $dst|$dst, $src2}",
48 "shl{q}\t{$src2, $dst|$dst, $src2}",
138 "shr{b}\t{$src2, $dst|$dst, $src2}",
141 "shr{w}\t{$src2, $dst|$dst, $src2}",
145 "shr{l}\t{$src2, $dst|$dst, $src2}",
149 "shr{q}\t{$src2, $dst|$dst, $src2}",
240 "sar{b}\t{$src2, $dst|$dst, $src2}",
243 "sar{w}\t{$src2, $dst|$dst, $src2}",
[all …]
H A DX86InstrKL.td20 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
21 "loadiwkey\t{$src2, $src1|$src1, $src2}",
22 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8XS,
41 "aesenc128kl\t{$src2, $src1|$src1, $src2}",
43 (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8XS,
47 "aesdec128kl\t{$src2, $src1|$src1, $src2}",
49 (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8XS,
53 "aesenc256kl\t{$src2, $src1|$src1, $src2}",
55 (X86aesenc256kl VR128:$src1, addr:$src2))]>, T8XS,
59 "aesdec256kl\t{$src2, $src1|$src1, $src2}",
[all …]
H A DX86InstrCMovSetCC.td21 "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
23 (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
27 "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
29 (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
33 "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
42 "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
43 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
47 "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
48 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
52 "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
[all …]
H A DX86InstrArithmetic.td155 "imul{w}\t{$src2, $dst|$dst, $src2}",
160 "imul{l}\t{$src2, $dst|$dst, $src2}",
166 "imul{q}\t{$src2, $dst|$dst, $src2}",
175 "imul{w}\t{$src2, $dst|$dst, $src2}",
181 "imul{l}\t{$src2, $dst|$dst, $src2}",
187 "imul{q}\t{$src2, $dst|$dst, $src2}",
645 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
679 mnemonic, "{$src2, $dst|$dst, $src2}", []>,
695 mnemonic, "{$src2, $src1|$src1, $src2}", []>,
708 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
[all …]
H A DX86InstrCompiler.td693 "{$src2, $dst|$dst, $src2}"),
700 "{$src2, $dst|$dst, $src2}"),
708 "{$src2, $dst|$dst, $src2}"),
716 "{$src2, $dst|$dst, $src2}"),
725 "{$src2, $dst|$dst, $src2}"),
733 "{$src2, $dst|$dst, $src2}"),
741 "{$src2, $dst|$dst, $src2}"),
749 "{$src2, $dst|$dst, $src2}"),
756 "{$src2, $dst|$dst, $src2}"),
764 "{$src2, $dst|$dst, $src2}"),
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dfdot2.ll29 %src2.vec = load <2 x half>, <2 x half> addrspace(1)* %src2
32 %src2.el1 = extractelement <2 x half> %src2.vec, i64 0
35 %src2.el2 = extractelement <2 x half> %src2.vec, i64 1
71 %src2.el1 = extractelement <2 x half> %src2.vec, i64 0
76 %src2.el2 = extractelement <2 x half> %src2.vec, i64 1
111 %src2.el1 = extractelement <2 x half> %src2.vec, i64 0
116 %src2.el2 = extractelement <2 x half> %src2.vec, i64 1
148 %src2.el1 = extractelement <4 x half> %src2.vec, i64 0
153 %src2.el2 = extractelement <4 x half> %src2.vec, i64 1
185 %src2.el1 = extractelement <2 x half> %src2.vec, i64 0
[all …]
H A Dmad-mix.ll14 %src2.ext = fpext half %src2 to float
26 %src2.hi = lshr i32 %src2, 16
29 %src2.i16 = trunc i32 %src2.hi to i16
32 %src2.fp16 = bitcast i16 %src2.i16 to half
35 %src2.ext = fpext half %src2.fp16 to float
51 %src2.ext = fpext half %src2.hi to float
111 %src2.ext = fpext half %src2 to float
125 %src2.ext = fpext half %src2 to float
144 %src2.ext = fpext half %src2 to float
175 %src2.neg = fneg float %src2
[all …]
H A Dllvm.amdgcn.fmed3.f16.ll5 …nel void @test_fmed3_f16(half addrspace(1)* %out, i32 %src0.arg, i32 %src1.arg, i32 %src2.arg) #1 {
10 %src2.f16 = trunc i32 %src2.arg to i16
11 %src2 = bitcast i16 %src2.f16 to half
12 %mad = call half @llvm.amdgcn.fmed3.f16(half %src0, half %src1, half %src2)
19 … @test_fmed3_srcmods_f16(half addrspace(1)* %out, i32 %src0.arg, i32 %src1.arg, i32 %src2.arg) #1 {
24 %src2.f16 = trunc i32 %src2.arg to i16
25 %src2 = bitcast i16 %src2.f16 to half
28 %src2.fabs = call half @llvm.fabs.f16(half %src2)
29 %src2.fneg.fabs = fsub half -0.0, %src2.fabs
30 %mad = call half @llvm.amdgcn.fmed3.f16(half %src0.fneg, half %src1.fabs, half %src2.fneg.fabs)
H A Dmad-mix-hi.ll12 %src2.ext = fpext half %src2 to float
13 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
28 %src2.ext = fpext half %src2 to float
29 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
43 %src2.ext = fpext half %src2 to float
56 define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, half %src2) #0 {
59 %src2.ext = fpext half %src2 to float
76 %src2.ext = fpext half %src2 to float
93 %src2.ext = fpext half %src2 to float
109 %src2.ext = fpext half %src2 to float
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-st2.mir18 ; CHECK: %src2:fpr64 = COPY $d1
24 %src2:fpr(<8 x s8>) = COPY $d1
43 ; CHECK: %src2:fpr128 = COPY $q1
49 %src2:fpr(<16 x s8>) = COPY $q1
68 ; CHECK: %src2:fpr64 = COPY $d1
74 %src2:fpr(<4 x s16>) = COPY $d1
99 %src2:fpr(<8 x s16>) = COPY $q1
117 ; CHECK: %src2:fpr64 = COPY $d1
195 %src2:fpr(<2 x p0>) = COPY $q1
219 %src2:gpr(s64) = COPY $x1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dpostlegalizer-combiner-divrem.mir16 ; CHECK-NEXT: %src2:_(s32) = COPY $vgpr1
24 %src2:_(s32) = COPY $vgpr1
43 ; CHECK-NEXT: %src2:_(s32) = COPY $vgpr1
51 %src2:_(s32) = COPY $vgpr1
70 ; CHECK-NEXT: %src2:_(s32) = COPY $vgpr1
78 %src2:_(s32) = COPY $vgpr1
105 %src2:_(s32) = COPY $vgpr1
132 %src2:_(<2 x s32>) = COPY $vgpr2_vgpr3
159 %src2:_(<2 x s32>) = COPY $vgpr2_vgpr3
189 %src2:_(s32) = COPY $vgpr1
[all …]
H A Dprelegalizer-combiner-divrem.mir21 %src2:_(s32) = COPY $vgpr1
96 %src2:_(s32) = COPY $vgpr1
171 %src2:_(s32) = COPY $vgpr1
246 %src2:_(s32) = COPY $vgpr1
325 %src2:_(s32) = COPY $vgpr1
359 %src2:_(s32) = COPY $vgpr1
392 %src2:_(s32) = COPY $vgpr1
423 %src2:_(s32) = COPY $vgpr1
450 %src2:_(s32) = COPY $vgpr1
476 %src2:_(s32) = COPY $vgpr1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-bitarith.ll10 %0 = and <16 x i8> %src1, %src2
20 %0 = and <8 x i16> %src1, %src2
30 %0 = and <4 x i32> %src1, %src2
40 %0 = and <2 x i64> %src1, %src2
51 %0 = or <16 x i8> %src1, %src2
61 %0 = or <8 x i16> %src1, %src2
174 %1 = and <16 x i8> %src2, %0
219 %1 = or <16 x i8> %src2, %0
230 %1 = or <8 x i16> %src2, %0
241 %1 = or <4 x i32> %src2, %0
[all …]
H A Dmve-vhaddsub.ll11 %0 = add <16 x i8> %src1, %src2
23 %0 = add <8 x i16> %src1, %src2
46 %0 = add <16 x i8> %src1, %src2
58 %0 = add <8 x i16> %src1, %src2
82 %0 = sub <16 x i8> %src1, %src2
94 %0 = sub <8 x i16> %src1, %src2
117 %0 = sub <16 x i8> %src1, %src2
129 %0 = sub <8 x i16> %src1, %src2
157 %0 = add <16 x i8> %src1, %src2
171 %0 = add <8 x i16> %src1, %src2
[all …]
H A Dmve-saturating-arith.ll4 define arm_aapcs_vfpcc <16 x i8> @sadd_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
10 %0 = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
20 %0 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
30 %0 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
296 declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
297 declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
298 declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
299 declare <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
300 declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
301 declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
[all …]
/llvm-project-15.0.7/libc/AOR_v20.02/string/arm/
H A Dstrcmp.S58 #define src2 r1 macro
141 ldrb r3, [src2]
151 orr tmp1, src1, src2
169 bic src2, src2, #7
260 bic src2, src2, #3
273 sub src2, src2, tmp1
299 add src2, src2, #4
327 add src2, src2, #4
336 bic src2, src2, #3
403 ldrh data2, [src2]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dmemcmp-nobuiltin.ll9 define i32 @f1(i8 *%src1, i8 *%src2) {
19 define i32 @f2(i8 *%src1, i8 *%src2) {
29 define void @f3(i8 *%src1, i8 *%src2, i32 *%dest) {
47 define void @f4(i8 *%src1, i8 *%src2, i32 *%dest) {
66 define void @f5(i8 *%src1, i8 *%src2, i32 *%dest) {
105 define i32 @f7(i8 *%src1, i8 *%src2, i32 *%dest) {
124 define i32 @f8(i8 *%src1, i8 *%src2) {
153 define i32 @f10(i8 *%src1, i8 *%src2) {
163 define i32 @f11(i8 *%src1, i8 *%src2) {
173 define i32 @f12(i8 *%src1, i8 *%src2) {
[all …]
H A Dmemcmp-01.ll8 define i32 @f1(i8 *%src1, i8 *%src2) {
12 %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 0)
17 define i32 @f2(i8 *%src1, i8 *%src2) {
29 define void @f3(i8 *%src1, i8 *%src2, i32 *%dest) {
47 define void @f4(i8 *%src1, i8 *%src2, i32 *%dest) {
66 define void @f5(i8 *%src1, i8 *%src2, i32 *%dest) {
127 define i32 @f8(i8 *%src1, i8 *%src2) {
162 define i32 @f10(i8 *%src1, i8 *%src2) {
175 define i32 @f11(i8 *%src1, i8 *%src2) {
190 define i32 @f12(i8 *%src1, i8 *%src2) {
[all …]

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