Lines Matching refs:src2
154 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
155 "imul{w}\t{$src2, $dst|$dst, $src2}",
157 (X86smul_flag GR16:$src1, GR16:$src2))]>,
159 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
160 "imul{l}\t{$src2, $dst|$dst, $src2}",
162 (X86smul_flag GR32:$src1, GR32:$src2))]>,
165 (ins GR64:$src1, GR64:$src2),
166 "imul{q}\t{$src2, $dst|$dst, $src2}",
168 (X86smul_flag GR64:$src1, GR64:$src2))]>,
174 (ins GR16:$src1, i16mem:$src2),
175 "imul{w}\t{$src2, $dst|$dst, $src2}",
177 (X86smul_flag GR16:$src1, (loadi16 addr:$src2)))]>,
180 (ins GR32:$src1, i32mem:$src2),
181 "imul{l}\t{$src2, $dst|$dst, $src2}",
183 (X86smul_flag GR32:$src1, (loadi32 addr:$src2)))]>,
186 (ins GR64:$src1, i64mem:$src2),
187 "imul{q}\t{$src2, $dst|$dst, $src2}",
189 (X86smul_flag GR64:$src1, (loadi64 addr:$src2)))]>,
202 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
203 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
205 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
208 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
209 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
211 (X86smul_flag GR16:$src1, imm:$src2))]>,
214 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
215 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
217 (X86smul_flag GR32:$src1, imm:$src2))]>,
220 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
223 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>,
226 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
227 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>,
232 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
235 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>,
240 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
241 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 i16immSExt8:$src2))]>,
247 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
248 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
250 (X86smul_flag (loadi16 addr:$src1), imm:$src2))]>,
253 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
254 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
257 i32immSExt8:$src2))]>,
260 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
261 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
263 (X86smul_flag (loadi32 addr:$src1), imm:$src2))]>,
266 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
267 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
270 i64immSExt8:$src2))]>,
273 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
274 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
277 i64immSExt32:$src2))]>,
644 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
645 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
654 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
662 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
670 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
678 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
679 mnemonic, "{$src2, $dst|$dst, $src2}", []>,
694 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
695 mnemonic, "{$src2, $src1|$src1, $src2}", []>,
707 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
708 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
716 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
717 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
729 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
736 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
743 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2),
750 (ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
751 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
761 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
768 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
774 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2,
781 (ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
782 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
792 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
799 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
806 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2,
1212 (ins GR8_NOREX:$src1, GR8_NOREX:$src2),
1213 "xor{b}\t{$src2, $dst|$dst, $src2}", []>,
1228 def : Pat<(X86adc_flag (loadi8 addr:$src2), GR8:$src1, EFLAGS),
1229 (ADC8rm GR8:$src1, addr:$src2)>;
1230 def : Pat<(X86adc_flag (loadi16 addr:$src2), GR16:$src1, EFLAGS),
1231 (ADC16rm GR16:$src1, addr:$src2)>;
1232 def : Pat<(X86adc_flag (loadi32 addr:$src2), GR32:$src1, EFLAGS),
1233 (ADC32rm GR32:$src1, addr:$src2)>;
1234 def : Pat<(X86adc_flag (loadi64 addr:$src2), GR64:$src1, EFLAGS),
1235 (ADC64rm GR64:$src1, addr:$src2)>;
1253 def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2),
1254 (!cast<Instruction>(NAME#"8ri") GR8:$src1, relocImm8_su:$src2)>;
1255 def : Pat<(OpNodeFlag GR16:$src1, i16relocImmSExt8_su:$src2),
1256 (!cast<Instruction>(NAME#"16ri8") GR16:$src1, i16relocImmSExt8_su:$src2)>;
1257 def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2),
1258 (!cast<Instruction>(NAME#"16ri") GR16:$src1, relocImm16_su:$src2)>;
1259 def : Pat<(OpNodeFlag GR32:$src1, i32relocImmSExt8_su:$src2),
1260 (!cast<Instruction>(NAME#"32ri8") GR32:$src1, i32relocImmSExt8_su:$src2)>;
1261 def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2),
1262 (!cast<Instruction>(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>;
1263 def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt8_su:$src2),
1264 (!cast<Instruction>(NAME#"64ri8") GR64:$src1, i64relocImmSExt8_su:$src2)>;
1265 def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2),
1266 (!cast<Instruction>(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>;
1285 def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2, EFLAGS),
1286 (!cast<Instruction>(NAME#"8ri") GR8:$src1, relocImm8_su:$src2)>;
1287 def : Pat<(OpNodeFlag GR16:$src1, i16relocImmSExt8_su:$src2, EFLAGS),
1288 (!cast<Instruction>(NAME#"16ri8") GR16:$src1, i16relocImmSExt8_su:$src2)>;
1289 def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2, EFLAGS),
1290 (!cast<Instruction>(NAME#"16ri") GR16:$src1, relocImm16_su:$src2)>;
1291 def : Pat<(OpNodeFlag GR32:$src1, i32relocImmSExt8_su:$src2, EFLAGS),
1292 (!cast<Instruction>(NAME#"32ri8") GR32:$src1, i32relocImmSExt8_su:$src2)>;
1293 def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2, EFLAGS),
1294 (!cast<Instruction>(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>;
1295 def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt8_su:$src2, EFLAGS),
1296 (!cast<Instruction>(NAME#"64ri8") GR64:$src1, i64relocImmSExt8_su:$src2)>;
1297 def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2, EFLAGS),
1298 (!cast<Instruction>(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>;
1317 def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2),
1318 (!cast<Instruction>(NAME#"8ri") GR8:$src1, relocImm8_su:$src2)>;
1319 def : Pat<(OpNodeFlag GR16:$src1, i16relocImmSExt8_su:$src2),
1320 (!cast<Instruction>(NAME#"16ri8") GR16:$src1, i16relocImmSExt8_su:$src2)>;
1321 def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2),
1322 (!cast<Instruction>(NAME#"16ri") GR16:$src1, relocImm16_su:$src2)>;
1323 def : Pat<(OpNodeFlag GR32:$src1, i32relocImmSExt8_su:$src2),
1324 (!cast<Instruction>(NAME#"32ri8") GR32:$src1, i32relocImmSExt8_su:$src2)>;
1325 def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2),
1326 (!cast<Instruction>(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>;
1327 def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt8_su:$src2),
1328 (!cast<Instruction>(NAME#"64ri8") GR64:$src1, i64relocImmSExt8_su:$src2)>;
1329 def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2),
1330 (!cast<Instruction>(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>;
1332 def : Pat<(OpNodeFlag (loadi8 addr:$src1), relocImm8_su:$src2),
1333 (!cast<Instruction>(NAME#"8mi") addr:$src1, relocImm8_su:$src2)>;
1334 def : Pat<(OpNodeFlag (loadi16 addr:$src1), i16relocImmSExt8_su:$src2),
1335 (!cast<Instruction>(NAME#"16mi8") addr:$src1, i16relocImmSExt8_su:$src2)>;
1336 def : Pat<(OpNodeFlag (loadi16 addr:$src1), relocImm16_su:$src2),
1337 (!cast<Instruction>(NAME#"16mi") addr:$src1, relocImm16_su:$src2)>;
1338 def : Pat<(OpNodeFlag (loadi32 addr:$src1), i32relocImmSExt8_su:$src2),
1339 (!cast<Instruction>(NAME#"32mi8") addr:$src1, i32relocImmSExt8_su:$src2)>;
1340 def : Pat<(OpNodeFlag (loadi32 addr:$src1), relocImm32_su:$src2),
1341 (!cast<Instruction>(NAME#"32mi") addr:$src1, relocImm32_su:$src2)>;
1342 def : Pat<(OpNodeFlag (loadi64 addr:$src1), i64relocImmSExt8_su:$src2),
1343 (!cast<Instruction>(NAME#"64mi8") addr:$src1, i64relocImmSExt8_su:$src2)>;
1344 def : Pat<(OpNodeFlag (loadi64 addr:$src1), i64relocImmSExt32_su:$src2),
1345 (!cast<Instruction>(NAME#"64mi32") addr:$src1, i64relocImmSExt32_su:$src2)>;
1361 def : Pat<(X86adc_flag GR8:$src1, relocImm8_su:$src2, EFLAGS),
1362 (ADC8ri relocImm8_su:$src2, GR8:$src1)>;
1363 def : Pat<(X86adc_flag i16relocImmSExt8_su:$src2, GR16:$src1, EFLAGS),
1364 (ADC16ri8 GR16:$src1, i16relocImmSExt8_su:$src2)>;
1365 def : Pat<(X86adc_flag relocImm16_su:$src2, GR16:$src1, EFLAGS),
1366 (ADC16ri GR16:$src1, relocImm16_su:$src2)>;
1367 def : Pat<(X86adc_flag i32relocImmSExt8_su:$src2, GR32:$src1, EFLAGS),
1368 (ADC32ri8 GR32:$src1, i32relocImmSExt8_su:$src2)>;
1369 def : Pat<(X86adc_flag relocImm32_su:$src2, GR32:$src1, EFLAGS),
1370 (ADC32ri GR32:$src1, relocImm32_su:$src2)>;
1371 def : Pat<(X86adc_flag i64relocImmSExt8_su:$src2, GR64:$src1, EFLAGS),
1372 (ADC64ri8 GR64:$src1, i64relocImmSExt8_su:$src2)>;
1373 def : Pat<(X86adc_flag i64relocImmSExt32_su:$src2, GR64:$src1, EFLAGS),
1374 (ADC64ri32 GR64:$src1, i64relocImmSExt32_su:$src2)>;
1441 def : Pat<(X86testpat GR8:$src1, relocImm8_su:$src2),
1442 (TEST8ri GR8:$src1, relocImm8_su:$src2)>;
1443 def : Pat<(X86testpat GR16:$src1, relocImm16_su:$src2),
1444 (TEST16ri GR16:$src1, relocImm16_su:$src2)>;
1445 def : Pat<(X86testpat GR32:$src1, relocImm32_su:$src2),
1446 (TEST32ri GR32:$src1, relocImm32_su:$src2)>;
1447 def : Pat<(X86testpat GR64:$src1, i64relocImmSExt32_su:$src2),
1448 (TEST64ri32 GR64:$src1, i64relocImmSExt32_su:$src2)>;
1450 def : Pat<(X86testpat (loadi8 addr:$src1), relocImm8_su:$src2),
1451 (TEST8mi addr:$src1, relocImm8_su:$src2)>;
1452 def : Pat<(X86testpat (loadi16 addr:$src1), relocImm16_su:$src2),
1453 (TEST16mi addr:$src1, relocImm16_su:$src2)>;
1454 def : Pat<(X86testpat (loadi32 addr:$src1), relocImm32_su:$src2),
1455 (TEST32mi addr:$src1, relocImm32_su:$src2)>;
1456 def : Pat<(X86testpat (loadi64 addr:$src1), i64relocImmSExt32_su:$src2),
1457 (TEST64mi32 addr:$src1, i64relocImmSExt32_su:$src2)>;
1464 def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1465 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1466 [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>,
1468 def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1469 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1471 (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>,
1482 def : Pat<(and (not GR32:$src1), GR32:$src2),
1483 (ANDN32rr GR32:$src1, GR32:$src2)>;
1484 def : Pat<(and (not GR64:$src1), GR64:$src2),
1485 (ANDN64rr GR64:$src1, GR64:$src2)>;
1486 def : Pat<(and (not GR32:$src1), (loadi32 addr:$src2)),
1487 (ANDN32rm GR32:$src1, addr:$src2)>;
1488 def : Pat<(and (not GR64:$src1), (loadi64 addr:$src2)),
1489 (ANDN64rm GR64:$src1, addr:$src2)>;
1539 (ins GR32:$src1, GR32:$src2),
1540 "adcx{l}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
1542 (ins GR64:$src1, GR64:$src2),
1543 "adcx{q}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
1546 (ins GR32:$src1, GR32:$src2),
1547 "adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
1550 (ins GR64:$src1, GR64:$src2),
1551 "adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
1561 (ins GR32:$src1, i32mem:$src2),
1562 "adcx{l}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
1565 (ins GR64:$src1, i64mem:$src2),
1566 "adcx{q}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
1569 (ins GR32:$src1, i32mem:$src2),
1570 "adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
1573 (ins GR64:$src1, i64mem:$src2),
1574 "adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS;