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/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Ddiv-by-0-guard-before-smul_ov.ll13 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
14 %smul.ov = extractvalue { i4, i1 } %smul, 1
26 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
27 %smul.ov = extractvalue { i4, i1 } %smul, 1
41 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size0, i4 %nmemb)
42 %smul.ov = extractvalue { i4, i1 } %smul, 1
56 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
57 %smul.ov = extractvalue { i4, i1 } %smul, 1
71 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
72 %smul.ov = extractvalue { i4, i1 } %smul, 1
[all …]
H A Ddiv-by-0-guard-before-smul_ov-not.ll14 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
15 %smul.ov = extractvalue { i4, i1 } %smul, 1
29 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
30 %smul.ov = extractvalue { i4, i1 } %smul, 1
46 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size0, i4 %nmemb)
47 %smul.ov = extractvalue { i4, i1 } %smul, 1
63 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
64 %smul.ov = extractvalue { i4, i1 } %smul, 1
80 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
81 %smul.ov = extractvalue { i4, i1 } %smul, 1
[all …]
H A Dsmul_fix.ll4 declare i16 @llvm.smul.fix.i16(i16, i16, i32)
5 declare i16 @llvm.smul.fix.sat.i16(i16, i16, i32)
6 declare <2 x i16> @llvm.smul.fix.v2i16(<2 x i16>, <2 x i16>, i32)
10 ;; llvm.smul.fix (scalar)
18 %res = call i16 @llvm.smul.fix.i16(i16 %arg, i16 0, i32 15)
27 %res = call i16 @llvm.smul.fix.i16(i16 0, i16 %arg, i32 15)
36 %res = call i16 @llvm.smul.fix.i16(i16 %arg, i16 undef, i32 15)
63 %res = call i16 @llvm.smul.fix.i16(i16 2, i16 %arg, i32 1)
68 ;; llvm.smul.fix.sat (scalar)
126 ;; llvm.smul.fix (vector)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Ddiv-by-0-guard-before-smul_ov.ll13 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
14 %smul.ov = extractvalue { i4, i1 } %smul, 1
27 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
28 %smul.ov = extractvalue { i4, i1 } %smul, 1
42 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size0, i4 %nmemb)
43 %smul.ov = extractvalue { i4, i1 } %smul, 1
57 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
58 %smul.ov = extractvalue { i4, i1 } %smul, 1
72 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
73 %smul.ov = extractvalue { i4, i1 } %smul, 1
[all …]
H A Ddiv-by-0-guard-before-smul_ov-not.ll15 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
16 %smul.ov = extractvalue { i4, i1 } %smul, 1
30 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
31 %smul.ov = extractvalue { i4, i1 } %smul, 1
47 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size0, i4 %nmemb)
48 %smul.ov = extractvalue { i4, i1 } %smul, 1
64 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
65 %smul.ov = extractvalue { i4, i1 } %smul, 1
81 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
82 %smul.ov = extractvalue { i4, i1 } %smul, 1
[all …]
H A Dsmulo.ll4 declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64)
5 declare { i8, i1 } @llvm.smul.with.overflow.i8(i8, i8)
13 %res = tail call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %a, i64 %b)
22 %res = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 0)
31 %res = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 1)
42 %res = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 2)
53 %res = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 3)
64 %res = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 4)
76 %res = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 127)
86 %res = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 128)
[all …]
H A Dcommutative-intrinsics.ll42 ; CHECK-NEXT: [[R:%.*]] = call i35 @llvm.smul.fix.i35(i35 [[X:%.*]], i35 42, i32 2)
45 %r = call i35 @llvm.smul.fix.i35(i35 42, i35 %x, i32 2)
60 ; CHECK-NEXT: [[R:%.*]] = call <2 x i35> @llvm.smul.fix.sat.v2i35(<2 x i35> [[X:%.*]], <2 x i35>…
63 %r = call <2 x i35> @llvm.smul.fix.sat.v2i35(<2 x i35> <i35 42, i35 43>, <2 x i35> %x, i32 4)
80 declare i35 @llvm.smul.fix.i35(i35, i35, i32)
82 declare <2 x i35> @llvm.smul.fix.sat.v2i35(<2 x i35>, <2 x i35>, i32)
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Dmuloti4.ll3 ; Test that 128-bit smul.with.overflow assembles as expected.
9 %smul = tail call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %a, i128 %b)
10 %cmp = extractvalue { i128, i1 } %smul, 1
11 %smul.result = extractvalue { i128, i1 } %smul, 0
12 %X = select i1 %cmp, i128 %smul.result, i128 42
18 declare { i128, i1 } @llvm.smul.with.overflow.i128(i128, i128) nounwind readnone
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/
H A Darith-fix.ll34 define i32 @smul(i32 %arg) {
35 ; SSSE3-LABEL: 'smul'
54 ; SSE42-LABEL: 'smul'
73 ; AVX1-LABEL: 'smul'
92 ; AVX2-LABEL: 'smul'
111 ; AVX512F-LABEL: 'smul'
130 ; AVX512BW-LABEL: 'smul'
149 ; AVX512DQ-LABEL: 'smul'
168 ; SLM-LABEL: 'smul'
187 ; GLM-LABEL: 'smul'
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Doverflow.ll150 ;; smul
154 %smul = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 %b)
155 %cmp = extractvalue { i8, i1 } %smul, 1
156 %smul.result = extractvalue { i8, i1 } %smul, 0
157 %X = select i1 %cmp, i8 %smul.result, i8 42
165 %smul = tail call { i16, i1 } @llvm.smul.with.overflow.i16(i16 %a, i16 %b)
166 %cmp = extractvalue { i16, i1 } %smul, 1
167 %smul.result = extractvalue { i16, i1 } %smul, 0
176 %smul = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %a, i32 %b)
177 %cmp = extractvalue { i32, i1 } %smul, 1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/
H A Dsmul-fix.ll8 declare i32 @llvm.smul.fix.i32(i32, i32, i32)
46 %r = call <8 x i3> @llvm.smul.fix.v8i3(
57 %r = call <8 x i3> @llvm.smul.fix.v8i3(
68 %r = call <8 x i3> @llvm.smul.fix.v8i3(
79 %r = call <8 x i3> @llvm.smul.fix.v8i3(
90 %r = call <8 x i3> @llvm.smul.fix.v8i3(
101 %r = call <8 x i3> @llvm.smul.fix.v8i3(
112 %r = call <8 x i3> @llvm.smul.fix.v8i3(
123 %r = call <8 x i3> @llvm.smul.fix.v8i3(
134 %r = call <8 x i3> @llvm.smul.fix.v8i3(
[all …]
H A Dsmul-fix-sat.ll8 declare i32 @llvm.smul.fix.sat.i32(i32, i32, i32)
45 %r = call <8 x i3> @llvm.smul.fix.sat.v8i3(
56 %r = call <8 x i3> @llvm.smul.fix.sat.v8i3(
67 %r = call <8 x i3> @llvm.smul.fix.sat.v8i3(
78 %r = call <8 x i3> @llvm.smul.fix.sat.v8i3(
89 %r = call <8 x i3> @llvm.smul.fix.sat.v8i3(
100 %r = call <8 x i3> @llvm.smul.fix.sat.v8i3(
111 %r = call <8 x i3> @llvm.smul.fix.sat.v8i3(
122 %r = call <8 x i3> @llvm.smul.fix.sat.v8i3(
133 %r = call <8 x i3> @llvm.smul.fix.sat.v8i3(
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Darith-mul-smulo.ll23 declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64)
24 declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32)
25 declare {i16, i1} @llvm.smul.with.overflow.i16(i16, i16)
26 declare {i8 , i1} @llvm.smul.with.overflow.i8 (i8 , i8 )
88 %c0 = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %a0, i64 %b0)
89 %c1 = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %a1, i64 %b1)
90 %c2 = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %a2, i64 %b2)
91 %c3 = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %a3, i64 %b3)
92 %c4 = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %a4, i64 %b4)
93 %c5 = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %a5, i64 %b5)
[all …]
H A Darith-fix.ll23 declare i64 @llvm.smul.fix.i64(i64, i64, i32)
24 declare i32 @llvm.smul.fix.i32(i32, i32, i32)
25 declare i16 @llvm.smul.fix.i16(i16, i16, i32)
26 declare i8 @llvm.smul.fix.i8 (i8 , i8 , i32)
131 %r0 = call i64 @llvm.smul.fix.i64(i64 %a0, i64 %b0, i32 3)
132 %r1 = call i64 @llvm.smul.fix.i64(i64 %a1, i64 %b1, i32 3)
133 %r2 = call i64 @llvm.smul.fix.i64(i64 %a2, i64 %b2, i32 3)
134 %r3 = call i64 @llvm.smul.fix.i64(i64 %a3, i64 %b3, i32 3)
135 %r4 = call i64 @llvm.smul.fix.i64(i64 %a4, i64 %b4, i32 3)
136 %r5 = call i64 @llvm.smul.fix.i64(i64 %a5, i64 %b5, i32 3)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dsmul_fix_sat_constants.ll6 declare i4 @llvm.smul.fix.sat.i4 (i4, i4, i32)
7 declare i32 @llvm.smul.fix.sat.i32 (i32, i32, i32)
8 declare i64 @llvm.smul.fix.sat.i64 (i64, i64, i32)
9 declare <4 x i32> @llvm.smul.fix.sat.v4i32(<4 x i32>, <4 x i32>, i32)
10 declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64)
26 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 3, i64 2, i32 2)
38 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 3, i64 2, i32 0)
56 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 9223372036854775807, i64 2, i32 2)
74 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 9223372036854775807, i64 2, i32 32)
94 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 9223372036854775807, i64 2, i32 63)
H A Dmulfix_combine.ll4 declare i32 @llvm.smul.fix.i32(i32, i32, i32 immarg)
6 declare i32 @llvm.smul.fix.sat.i32(i32, i32, i32 immarg)
9 declare <4 x i32> @llvm.smul.fix.v4i32(<4 x i32>, <4 x i32>, i32 immarg)
11 declare <4 x i32> @llvm.smul.fix.sat.v4i32(<4 x i32>, <4 x i32>, i32 immarg)
19 %tmp = call i32 @llvm.smul.fix.i32(i32 undef, i32 %y, i32 2)
28 %tmp = call i32 @llvm.smul.fix.i32(i32 0, i32 %y, i32 2)
55 %tmp = call i32 @llvm.smul.fix.sat.i32(i32 undef, i32 %y, i32 2)
64 %tmp = call i32 @llvm.smul.fix.sat.i32(i32 0, i32 %y, i32 2)
91 %tmp = call <4 x i32> @llvm.smul.fix.v4i32(<4 x i32> undef, <4 x i32> %y, i32 2)
100 …%tmp = call <4 x i32> @llvm.smul.fix.v4i32(<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> %y, i…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dsmulo-sdnode.ll4 declare { <vscale x 1 x i8>, <vscale x 1 x i1> } @llvm.smul.with.overflow.nxv1i8(<vscale x 1 x i8>,…
16 …%a = call { <vscale x 1 x i8>, <vscale x 1 x i1> } @llvm.smul.with.overflow.nxv1i8(<vscale x 1 x i…
23 declare { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i8(<vscale x 2 x i8>,…
42 declare { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i8(<vscale x 4 x i8>,…
61 declare { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i8(<vscale x 8 x i8>,…
80 declare { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i8(<vscale x 16 x …
99 declare { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i8(<vscale x 32 x …
118 declare { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.smul.with.overflow.nxv64i8(<vscale x 64 x …
137 declare { <vscale x 1 x i16>, <vscale x 1 x i1> } @llvm.smul.with.overflow.nxv1i16(<vscale x 1 x i1…
156 declare { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i16(<vscale x 2 x i1…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Doverflow-intrinsic-optimizations.ll10 %1 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %0, i64 %b)
25 %0 = call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %a, i128 %b)
30 declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64)
31 declare { i128, i1 } @llvm.smul.with.overflow.i128(i128, i128)
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A D2011-07-07-MatchIntrinsicExtract.ll73 %smul = tail call %0 @llvm.smul.with.overflow.i64(i64 %a, i64 %b)
74 %smul.0 = extractvalue %0 %smul, 0
76 %add2 = add i64 %mul1, %smul.0
90 declare %0 @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A Doverflow-intrinsic-optimizations.ll3 declare { i128, i1 } @llvm.smul.with.overflow.i128(i128, i128)
4 declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64)
9 %mul4 = tail call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %a, i128 %b)
21 %mul4 = tail call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %a, i64 %b)
/llvm-project-15.0.7/llvm/test/Analysis/ValueTracking/
H A Dpr23011.ll3 declare { i8, i1 } @llvm.smul.with.overflow.i8(i8, i8) nounwind readnone
9 %t = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %rem, i8 %rem)
10 ; CHECK: %t = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %rem, i8 %rem)
/llvm-project-15.0.7/llvm/test/Transforms/GVN/
H A D2011-07-07-MatchIntrinsicExtract.ll68 %smul = tail call %0 @llvm.smul.with.overflow.i64(i64 %a, i64 %b)
69 %smul.0 = extractvalue %0 %smul, 0
84 declare %0 @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dbuiltins-overflow.cpp88 constexpr Result<int> smul(int lhs, int rhs) { in smul() function
93 static_assert(smul(17,22) == Result<int>{false, 374});
94 static_assert(smul(INT_MAX / 22, 23) == Result<int>{true, -2049870757});
95 static_assert(smul(INT_MIN / 22, -23) == Result<int>{true, -2049870757});
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dunschedule-first-call.ll27 %20 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %18, i64 %19)
31 %24 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %23, i64 undef)
48 %41 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %39, i64 %40)
53 %46 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %44, i64 %45)
69 %62 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %61, i64 undef)
76 %69 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %67, i64 %68)
123 declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64) #1
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-smulo-sdnode.ll4 declare { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i8(<vscale x 2 x i8>,…
23 …%a = call { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i8(<vscale x 2 x i…
30 declare { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i8(<vscale x 4 x i8>,…
56 declare { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i8(<vscale x 8 x i8>,…
82 declare { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i8(<vscale x 16 x …
103 declare { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i8(<vscale x 32 x …
130 declare { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.smul.with.overflow.nxv64i8(<vscale x 64 x …
170 declare { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i16(<vscale x 2 x i1…
196 declare { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i16(<vscale x 4 x i1…
222 declare { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i16(<vscale x 8 x i1…
[all …]

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