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/llvm-project-15.0.7/llvm/test/MC/VE/
H A DSLD.s6 # CHECK-INST: sld %s11, %s11, %s11
8 sld %s11, %s11, %s11 label
10 # CHECK-INST: sld %s11, %s11, 63
12 sld %s11, %s11, 63 label
14 # CHECK-INST: sld %s11, %s11, 127
16 sld %s11, %s11, 127 label
18 # CHECK-INST: sld %s11, %s11, 64
20 sld %s11, %s11, 64 label
22 # CHECK-INST: sld %s11, (32)1, 64
24 sld %s11, (32)1, 64 label
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dshift128.ll10 ; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]]
24 ; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]]
38 ; CHECK-DAG: sld [[R2:[0-9]+]], 4, 5
40 ; CHECK-DAG: sld [[R4:[0-9]+]], 3, [[R1]]
43 ; CHECK-DAG: sld 3, 3, 5
56 ; P9-NOT: {{\b}}sld
75 ; P9-NOT: {{\b}}sld
H A Dfunnel-shift.ll93 ; CHECK64-NEXT: sld 3, 3, 5
221 ; CHECK64-NEXT: sld 5, 6, 7
223 ; CHECK64-NEXT: sld 7, 3, 7
368 ; CHECK64-NEXT: sld 3, 3, 5
524 ; CHECK64-NEXT: sld 3, 3, 6
667 ; CHECK64-NEXT: sld 3, 3, 6
H A Duse-cr-result-of-dom-icmp-st.ll20 ; CHECK-NEXT: sld r5, r3, r4
49 ; CHECK-NEXT: sld r5, r3, r4
78 ; CHECK-NEXT: sld. r5, r3, r4
106 ; CHECK-NEXT: sld r5, r3, r4
135 ; CHECK-NEXT: sld r5, r3, r4
H A Doptcmp.ll203 ; CHECK-NEXT: sld 4, 3, 4
212 ; CHECK-NO-ISEL-NEXT: sld 4, 3, 4
H A Dshift_mask.ll42 ; CHECK-NEXT: sld 3, 3, 4
H A Dvsx.ll1791 ; CHECK-NEXT: sld r3, r4, r3
1795 ; CHECK-NEXT: sld r3, r4, r3
1809 ; CHECK-REG-NEXT: sld r3, r4, r3
1813 ; CHECK-REG-NEXT: sld r3, r4, r3
1827 ; CHECK-FISL-NEXT: sld r3, r3, r4
1831 ; CHECK-FISL-NEXT: sld r3, r3, r4
/llvm-project-15.0.7/llvm/test/MC/Mips/msa/
H A Dtest_3r.s193 # CHECK: sld.b $w5, $w23[$12] # encoding: [0x78,0x0c,0xb9,0x54]
194 # CHECK: sld.h $w1, $w23[$3] # encoding: [0x78,0x23,0xb8,0x54]
195 # CHECK: sld.w $w20, $w8[$9] # encoding: [0x78,0x49,0x45,0x14]
196 # CHECK: sld.d $w7, $w23[$fp] # encoding: [0x78,0x7e,0xb9,0xd4]
436 sld.b $w5, $w23[$12]
437 sld.h $w1, $w23[$3]
438 sld.w $w20, $w8[$9]
439 sld.d $w7, $w23[$30]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dbasic_operations_float.ll320 ; ALL-DAG: sld.b [[R1]], [[R1]][[[BIDX]]]
323 ; ALL-DAG: sld.b [[R1]], [[R1]][[[NIDX]]]
349 ; ALL-DAG: sld.b [[R1]], [[R1]][[[BIDX]]]
352 ; ALL-DAG: sld.b [[R1]], [[R1]][[[NIDX]]]
H A Dbasic_operations.ll1908 ; O32-NEXT: sld.b $w0, $w0[$2]
1911 ; O32-NEXT: sld.b $w0, $w0[$2]
1924 ; N32-NEXT: sld.b $w0, $w0[$2]
1927 ; N32-NEXT: sld.b $w0, $w0[$2]
1940 ; N64-NEXT: sld.b $w0, $w0[$2]
1943 ; N64-NEXT: sld.b $w0, $w0[$2]
1967 ; O32-NEXT: sld.b $w0, $w0[$2]
1970 ; O32-NEXT: sld.b $w0, $w0[$2]
1984 ; N32-NEXT: sld.b $w0, $w0[$2]
1987 ; N32-NEXT: sld.b $w0, $w0[$2]
[all …]
H A D3r-s.ll17 %3 = tail call <16 x i8> @llvm.mips.sld.b(<16 x i8> %0, <16 x i8> %1, i32 %2)
22 declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, <16 x i8>, i32) nounwind
31 ; CHECK-DAG: sld.b [[WD]], [[WS]][[[RT]]]
45 %3 = tail call <8 x i16> @llvm.mips.sld.h(<8 x i16> %0, <8 x i16> %1, i32 %2)
50 declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, <8 x i16>, i32) nounwind
59 ; CHECK-DAG: sld.h [[WD]], [[WS]][[[RT]]]
73 %3 = tail call <4 x i32> @llvm.mips.sld.w(<4 x i32> %0, <4 x i32> %1, i32 %2)
78 declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, <4 x i32>, i32) nounwind
87 ; CHECK-DAG: sld.w [[WD]], [[WS]][[[RT]]]
106 declare <2 x i64> @llvm.mips.sld.d(<2 x i64>, <2 x i64>, i32) nounwind
[all …]
/llvm-project-15.0.7/llvm/test/MC/PowerPC/
H A Dppc64-encoding.s994 # CHECK-BE: sld 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x36]
995 # CHECK-LE: sld 2, 3, 4 # encoding: [0x36,0x20,0x62,0x7c]
996 sld 2, 3, 4
997 # CHECK-BE: sld. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x37]
998 # CHECK-LE: sld. 2, 3, 4 # encoding: [0x37,0x20,0x62,0x7c]
999 sld. 2, 3, 4
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/msa/
H A Dtest_3r.txt193 0x78 0x0c 0xb9 0x54 # CHECK: sld.b $w5, $w23[$12]
194 0x78 0x23 0xb8 0x54 # CHECK: sld.h $w1, $w23[$3]
195 0x78 0x49 0x45 0x14 # CHECK: sld.w $w20, $w8[$9]
196 0x78 0x7e 0xb9 0xd4 # CHECK: sld.d $w7, $w23[$fp]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/PowerPC/
H A Dppc64le-encoding.txt760 # CHECK: sld 2, 3, 4
763 # CHECK: sld. 2, 3, 4
H A Dppc64-encoding.txt814 # CHECK: sld 2, 3, 4
817 # CHECK: sld. 2, 3, 4
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td292 // vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd],
H A DMipsMSAInstrInfo.td2552 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2553 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2554 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2555 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
H A DMipsScheduleGeneric.td1442 // vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd],
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstr64Bit.td894 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.td1328 defm SLD : RRILDm<"sld", 0x64, I64>;