[MIPS][MSA] Regenerate basic operations test checks

Cleanup the check prefixes to make refresh a lot easier

[mips] Remove -allow-deprecated-dag-overlap flag from tests. NFC

Fix DAG check statements in MIPS codegen tests to remove
-allow-deprecated-dag-overlap flag.

llvm-svn: 343730

[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests

See https://reviews.llvm.org/D47106 for details.

Reviewed By: probinson

Differential Revision: https://reviews.llvm.org/D47171

[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests

See https://reviews.llvm.org/D47106 for details.

Reviewed By: probinson

Differential Revision: https://reviews.llvm.org/D47171

This commit drops that patch's changes to:

llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
llvm/test/CodeGen/NVPTX/param-load-store.ll

For some reason, the dos line endings there prevent me from commiting
via the monorepo. A follow-up commit (not via the monorepo) will
finish the patch.

llvm-svn: 336843

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[mips][msa] Accept more values for constant splats

This patches teaches the MIPS backend to accept more values for constant
splats. Previously, only 10 bit signed immediates or values that could be

[mips][msa] Accept more values for constant splats

This patches teaches the MIPS backend to accept more values for constant
splats. Previously, only 10 bit signed immediates or values that could be
loaded using an ldi.[bhwd] instruction would be acceptted. This patch relaxes
that constraint so that any constant value that be splatted is accepted.

As a result, the constant pool is used less for vector operations, and the
suite of bit manipulation instructions b(clr|set|neg)i can now be used with
the full range of their immediate operand.

Reviewers: slthakur

Differential Revision: https://reviews.llvm.org/D30640

llvm-svn: 297457

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[mips] Correct label prefixes for N32 and N64.

Summary:
N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own
($).

This fixes the majority of object differences between -fin

[mips] Correct label prefixes for N32 and N64.

Summary:
N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own
($).

This fixes the majority of object differences between -fintegrated-as and
-fno-integrated-as.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D22412

llvm-svn: 275967

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[mips] Use --check-prefixes where appropriate. NFC.

llvm-svn: 273669

[mips][msa] Fix register/register-class mismatches in emitINSERT_DF_VIDX().

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D21068

l

[mips][msa] Fix register/register-class mismatches in emitINSERT_DF_VIDX().

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D21068

llvm-svn: 272765

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[mips] Make Static a default relocation model for MIPS codegen

This change follows up defaults for GCC and Clang, so LLVM does not differ
from them. While number of the test files are touched with t

[mips] Make Static a default relocation model for MIPS codegen

This change follows up defaults for GCC and Clang, so LLVM does not differ
from them. While number of the test files are touched with this change, they
all keep the old (expected) behaviour with the explicit option:
"-relocation-model=pic"
The tests that have not been touched are insensitive to relocation model.

Differential Revision: http://reviews.llvm.org/D17995

llvm-svn: 265949

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[mips] Generate code for insert/extract operations when using the N64 ABI and MSA.

Summary:
When using the N64 ABI, element-indices use the i64 type instead of i32.
In many cases, we can use iPTR to

[mips] Generate code for insert/extract operations when using the N64 ABI and MSA.

Summary:
When using the N64 ABI, element-indices use the i64 type instead of i32.
In many cases, we can use iPTR to account for this but additional patterns
and pseudo's are also required.

This fixes most (but not quite all) failures in the test-suite when using
N64 and MSA together.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9342

llvm-svn: 236494

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[mips][msa] Test basic operations for the N32 ABI too.

Summary:
This required adding instruction aliases for dneg.

N64 will be enabled shortly but requires additional bugfixes.

Reviewers: vkalinti

[mips][msa] Test basic operations for the N32 ABI too.

Summary:
This required adding instruction aliases for dneg.

N64 will be enabled shortly but requires additional bugfixes.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9341

llvm-svn: 236489

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[mips][msa] Rename main check prefix to 'ALL' in basic operations tests. NFC

Summary:
The majority of the checks are subtarget independent. The few that aren't
will be corrected shortly.

Reviewers:

[mips][msa] Rename main check prefix to 'ALL' in basic operations tests. NFC

Summary:
The majority of the checks are subtarget independent. The few that aren't
will be corrected shortly.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9340

llvm-svn: 236220

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[mips][msa] Use CHECK-LABEL where missing, and remove checks matching the .size directive. NFC.

Summary:

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential R

[mips][msa] Use CHECK-LABEL where missing, and remove checks matching the .size directive. NFC.

Summary:

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9339

llvm-svn: 236219

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[mips] Add missing signext attributes to MSA basic operations tests. NFC.

Summary:
This doesn't make much difference to MIPS32, but it will simplify a
MIPS64r6 bugfix which will follow shortly by re

[mips] Add missing signext attributes to MSA basic operations tests. NFC.

Summary:
This doesn't make much difference to MIPS32, but it will simplify a
MIPS64r6 bugfix which will follow shortly by removing unnecessary
sign-extension of parameters.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9338

llvm-svn: 236216

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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test

[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794

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[mips][msa] Fix vector insertions where the index is variable

Summary:
This isn't supported directly so we rotate the vector by the desired number of
elements, insert to element zero, then rotate ba

[mips][msa] Fix vector insertions where the index is variable

Summary:
This isn't supported directly so we rotate the vector by the desired number of
elements, insert to element zero, then rotate back.

The i64 case generates rather poor code on MIPS32. There is an obvious
optimisation to be made in future (do both insert.w's inside a shared
rotate/unrotate sequence) but for now it's sufficient to select valid code
instead of aborting.

Depends on D3536

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3537

llvm-svn: 207640

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[mips][msa] Use CHECK-LABEL in basic_operations*.ll

Differential Revision: http://reviews.llvm.org/D3536

llvm-svn: 207529

[mips][msa] Fix element extraction where the index is variable.

Summary:
This isn't supported directly so we splat the vector element and extract
the most convenient copy.

Reviewers: matheusalmeida

[mips][msa] Fix element extraction where the index is variable.

Summary:
This isn't supported directly so we splat the vector element and extract
the most convenient copy.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3530

llvm-svn: 207524

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[mips] Prevent %lo relocation being used on MSA loads and stores.

Summary:
Parts of the compiler still believed MSA load/stores have a 16-bit offset when
it is actually 10-bit. Corrected this, and f

[mips] Prevent %lo relocation being used on MSA loads and stores.

Summary:
Parts of the compiler still believed MSA load/stores have a 16-bit offset when
it is actually 10-bit. Corrected this, and fixed a closely related issue this
uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS
respectively) could not load/store using offsets from the stack/frame pointer.
They accepted frameindex+offset, but not frameindex by itself.

Reviewers: jacksprat, matheusalmeida

Reviewed By: jacksprat

Differential Revision: http://llvm-reviews.chandlerc.com/D2888

llvm-svn: 202717

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[mips][msa] Merge basic_operations_little.ll into basic_operations.ll.

Now that FileCheck supports multiple check prefixes, we don't need to keep the
little and big endian versions of this test sepa

[mips][msa] Merge basic_operations_little.ll into basic_operations.ll.

Now that FileCheck supports multiple check prefixes, we don't need to keep the
little and big endian versions of this test separate anymore. Merge them back
together.

llvm-svn: 194826

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[mips][msa] Build all the tests in little and big endian modes and correct an incorrect test.

Summary:
This patch (correctly) breaks some MSA tests by exposing the cases when
SelectionDAG::getConsta

[mips][msa] Build all the tests in little and big endian modes and correct an incorrect test.

Summary:
This patch (correctly) breaks some MSA tests by exposing the cases when
SelectionDAG::getConstant() produces illegal types. These have been temporarily
marked XFAIL and the XFAIL flag will be removed when
SelectionDAG::getConstant() is fixed.

There are three categories of failure:
* Immediate instructions are not selected in one endian mode.
* Immediates used in ldi.[bhwd] must be different according to endianness.
(this only affects cases where the 'wrong' ldi is used to load the correct
bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...)))
* Non-immediate instructions that rely on immediates affected by the
previous two categories as part of their match pattern.
For example, the bset match pattern is the vector equivalent of
'ws | (1 << wt)'.

One test needed correcting to expect different output depending on whether big
or little endian was in use. This test was
test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category
of failure shown above. The little endian version of this test is named
basic_operations_little.ll and will be merged back into basic_operations.ll in
a follow up commit now that FileCheck supports multiple check prefixes.

Reviewers: bkramer, jacksprat, dsanders

Reviewed By: dsanders

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1972

llvm-svn: 194806

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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

llvm-svn: 191498

[mips][msa] Expand all truncstores and loadexts for MSA as well as DSP

llvm-svn: 191496

[mips][msa] Non-constant BUILD_VECTOR's should be expanded to INSERT_VECTOR_ELT instead of memory operations.

The resulting code is the same length, but doesnt cause memory traffic or latency.

llvm

[mips][msa] Non-constant BUILD_VECTOR's should be expanded to INSERT_VECTOR_ELT instead of memory operations.

The resulting code is the same length, but doesnt cause memory traffic or latency.

llvm-svn: 191297

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[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics)

Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a sing

[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics)

Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
operation and implemented the DAG combines necessary to fold sign/zero
extends into the extract.

llvm-svn: 191199

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[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD)

Note: There's a later patch on my branch that re-implements this to select
build_vector witho

[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD)

Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).

Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
This is a special case of BUILD_VECTOR that covers the case the
BUILD_VECTOR is a splat operation.
* Added VSPLATD
This is a special case of VSPLAT that handles the cases when v2i64 is legal

llvm-svn: 191191

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