| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 122 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering()
123 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); in AVRTargetLowering()
124 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
125 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2370 void setIndexedStoreAction(ArrayRef<unsigned> IdxModes, MVT VT, in setIndexedStoreAction() function
2376 void setIndexedStoreAction(ArrayRef<unsigned> IdxModes, ArrayRef<MVT> VTs, in setIndexedStoreAction() function
2379 setIndexedStoreAction(IdxModes, VT, Action); in setIndexedStoreAction()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 765 setIndexedStoreAction(IM, VT, Expand); in initActions()
785 setIndexedStoreAction(IM, VT, Expand); in initActions()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 221 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
222 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
223 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
224 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
225 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
229 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
230 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 853 setIndexedStoreAction(im, MVT::i8, Legal); in AArch64TargetLowering()
854 setIndexedStoreAction(im, MVT::i16, Legal); in AArch64TargetLowering()
855 setIndexedStoreAction(im, MVT::i32, Legal); in AArch64TargetLowering()
856 setIndexedStoreAction(im, MVT::i64, Legal); in AArch64TargetLowering()
857 setIndexedStoreAction(im, MVT::f64, Legal); in AArch64TargetLowering()
858 setIndexedStoreAction(im, MVT::f32, Legal); in AArch64TargetLowering()
859 setIndexedStoreAction(im, MVT::f16, Legal); in AArch64TargetLowering()
860 setIndexedStoreAction(im, MVT::bf16, Legal); in AArch64TargetLowering()
1557 setIndexedStoreAction(im, VT, Legal); in addTypeForNEON()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 317 setIndexedStoreAction(im, VT, Legal); in addMVEVectorTypes()
347 setIndexedStoreAction(im, VT, Legal); in addMVEVectorTypes()
430 setIndexedStoreAction(im, VT, Legal); in addMVEVectorTypes()
1110 setIndexedStoreAction(im, MVT::i1, Legal); in ARMTargetLowering()
1111 setIndexedStoreAction(im, MVT::i8, Legal); in ARMTargetLowering()
1112 setIndexedStoreAction(im, MVT::i16, Legal); in ARMTargetLowering()
1113 setIndexedStoreAction(im, MVT::i32, Legal); in ARMTargetLowering()
1118 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); in ARMTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 164 setIndexedStoreAction(ISD::POST_INC, T, Legal); in initializeHVXLowering()
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| H A D | HexagonISelLowering.cpp | 1791 setIndexedStoreAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
|
| /llvm-project-15.0.7/llvm/docs/ |
| H A D | WritingAnLLVMBackend.rst | 1373 * ``setIndexedStoreAction`` --- Indexed store.
|