| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 118 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering()
119 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in AVRTargetLowering()
120 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
121 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2353 void setIndexedLoadAction(ArrayRef<unsigned> IdxModes, MVT VT, in setIndexedLoadAction() function
2359 void setIndexedLoadAction(ArrayRef<unsigned> IdxModes, ArrayRef<MVT> VTs, in setIndexedLoadAction() function
2362 setIndexedLoadAction(IdxModes, VT, Action); in setIndexedLoadAction()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 61 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
62 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 764 setIndexedLoadAction(IM, VT, Expand); in initActions()
784 setIndexedLoadAction(IM, VT, Expand); in initActions()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 216 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
217 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
218 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
219 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
220 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
227 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
228 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 845 setIndexedLoadAction(im, MVT::i8, Legal); in AArch64TargetLowering()
846 setIndexedLoadAction(im, MVT::i16, Legal); in AArch64TargetLowering()
847 setIndexedLoadAction(im, MVT::i32, Legal); in AArch64TargetLowering()
848 setIndexedLoadAction(im, MVT::i64, Legal); in AArch64TargetLowering()
849 setIndexedLoadAction(im, MVT::f64, Legal); in AArch64TargetLowering()
850 setIndexedLoadAction(im, MVT::f32, Legal); in AArch64TargetLowering()
851 setIndexedLoadAction(im, MVT::f16, Legal); in AArch64TargetLowering()
852 setIndexedLoadAction(im, MVT::bf16, Legal); in AArch64TargetLowering()
1556 setIndexedLoadAction(im, VT, Legal); in addTypeForNEON()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 316 setIndexedLoadAction(im, VT, Legal); in addMVEVectorTypes()
346 setIndexedLoadAction(im, VT, Legal); in addMVEVectorTypes()
429 setIndexedLoadAction(im, VT, Legal); in addMVEVectorTypes()
1106 setIndexedLoadAction(im, MVT::i1, Legal); in ARMTargetLowering()
1107 setIndexedLoadAction(im, MVT::i8, Legal); in ARMTargetLowering()
1108 setIndexedLoadAction(im, MVT::i16, Legal); in ARMTargetLowering()
1109 setIndexedLoadAction(im, MVT::i32, Legal); in ARMTargetLowering()
1117 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); in ARMTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 163 setIndexedLoadAction(ISD::POST_INC, T, Legal); in initializeHVXLowering()
|
| H A D | HexagonISelLowering.cpp | 1790 setIndexedLoadAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
|
| /llvm-project-15.0.7/llvm/docs/ |
| H A D | WritingAnLLVMBackend.rst | 1372 * ``setIndexedLoadAction`` --- Indexed load.
|