Home
last modified time | relevance | path

Searched refs:selection (Results 1 – 25 of 283) sorted by relevance

12345678910>>...12

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Darm-unsupported.ll12 ; CHECK-LABEL: warning: Instruction selection used fallback path for test_int_vectors
19 ; CHECK-LABEL: warning: Instruction selection used fallback path for test_float_vectors
26 ; CHECK-LABEL: warning: Instruction selection used fallback path for test_i64
33 ; CHECK-LABEL: warning: Instruction selection used fallback path for test_i64_arr
39 ; CHECK-LABEL: warning: Instruction selection used fallback path for test_i128
46 ; CHECK-LABEL: warning: Instruction selection used fallback path for test_funny_ints
53 ; CHECK-LABEL: warning: Instruction selection used fallback path for test_half
62 ; CHECK-LABEL: warning: Instruction selection used fallback path for test_ret_demotion
82 ; CHECK-LABEL: warning: Instruction selection used fallback path for test_mixed_struct
102 ; CHECK-LABEL: warning: Instruction selection used fallback path for test_thumb
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfmf-propagation.ll21 ; FMFDEBUG: Type-legalized selection DAG: %bb.0 'fmul_fadd_contract1:'
133 ; FMFDEBUG: Type-legalized selection DAG: %bb.0 'fmul_fadd_fast1:'
156 ; FMFDEBUG: Type-legalized selection DAG: %bb.0 'fmul_fadd_fast2:'
238 ; FMFDEBUG: Type-legalized selection DAG: %bb.0 'fmul_fma_fast1:'
267 ; FMFDEBUG: Type-legalized selection DAG: %bb.0 'fmul_fma_fast2:'
296 ; FMFDEBUG: Type-legalized selection DAG: %bb.0 'sqrt_afn_ieee:'
434 ; FMFDEBUG: Type-legalized selection DAG: %bb.0 'sqrt_fast_ieee:'
542 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fcmp_nnan:'
544 ; FMFDEBUG: Type-legalized selection DAG: %bb.0 'fcmp_nnan:'
548 ; GLOBALDEBUG: Type-legalized selection DAG: %bb.0 'fcmp_nnan:'
[all …]
H A Dadd_cmp.ll12 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiUnsigned:entry'
25 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiSigned:entry'
38 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiUnsignedOverflow:entry'
51 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiSignedOverflow:entry'
/llvm-project-15.0.7/mlir/test/Target/SPIRV/
H A Dselection.mlir6 // CHECK-LABEL: @selection
7 spv.func @selection(%cond: i1) -> () "None" {
17 // CHECK-NEXT: spv.mlir.selection control(Flatten)
18 spv.mlir.selection control(Flatten) {
60 // CHECK-LABEL: spv.func @selection
62 spv.func @selection(%cond: i1) -> (i32) "None" {
65 // CHECK-NEXT: spv.mlir.selection
66 spv.mlir.selection {
95 // SSA value def before selection and use after selection
109 // CHECK-NEXT: spv.mlir.selection {
[all …]
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Ddebuginfo-properties.m13 @property (nonatomic, retain) Selection* selection; property
22 @synthesize selection = _selection;
23 // CHECK: !DISubprogram(name: "-[MyClass selection]"
36 @synthesize selection = _selection;
37 // CHECK: !DISubprogram(name: "-[OtherClass selection]"
/llvm-project-15.0.7/clang/tools/clang-format/
H A Dclang-format-bbedit.applescript4 -- selection. Note that you can rename the menu item by renaming the script, and
12 set selectionOffset to characterOffset of selection
13 set selectionLength to length of selection
22 -- replacing a selection flashes a bit but doesn't affect the scroll position.
25 set text of selection to newContents
/llvm-project-15.0.7/polly/lib/External/isl/
H A Disl_vertices.c270 int *selection) in can_select() argument
426 int *selection = NULL; in isl_basic_set_compute_vertices() local
500 selection); in isl_basic_set_compute_vertices()
530 free(selection); in isl_basic_set_compute_vertices()
543 free(selection); in isl_basic_set_compute_vertices()
670 if (selection[i]) in add_chamber()
700 if (selection[i]) { in add_chamber()
960 if (!selection[i]) in compute_chambers()
993 if (!selection[i]) in compute_chambers()
1019 free(selection); in compute_chambers()
[all …]
/llvm-project-15.0.7/mlir/include/mlir/Dialect/SPIRV/IR/
H A DSPIRVControlFlowOps.td323 We use `spv.mlir.selection`/`spv.mlir.loop` for modelling structured selection/loop.
421 def SPV_SelectionOp : SPV_Op<"mlir.selection", [InFunctionScope]> {
422 let summary = "Define a structured selection.";
436 the selection and it plays nicer with the MLIR system.
438 The `spv.mlir.selection` region should contain at least two blocks: one selection
439 header block, and one selection merge. The selection header block should be
440 the first block. The selection merge block should be the last block.
453 /// Returns the selection header block.
456 /// Returns the selection merge block.
459 /// Adds a selection merge block containing one spv.mlir.merge op.
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dcombine_loads_from_build_pair.ll6 ; between "Initial selection DAG" and "Optimized lowered selection DAG".
10 ; CHECK-LABEL: Initial selection DAG:
18 ; CHECK-LABEL: Optimized lowered selection DAG:
/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/IR/
H A Dcontrol-flow-ops.mlir445 spv.mlir.selection {
487 spv.mlir.selection {
542 spv.mlir.selection {
570 spv.mlir.selection {
640 spv.mlir.selection {
657 // spv.mlir.selection
666 spv.mlir.selection {
694 spv.mlir.selection {
724 spv.mlir.selection {
743 spv.mlir.selection {
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dmapped_intrinsics.ll21 ; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.r.rnd.goodsyntax
33 ; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.r.rnd.goodsyntax
43 ; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.p.rnd.goodsyntax
56 ; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.p.rnd.goodsyntax
67 ; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax
79 ; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax
89 ; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.vasrhrnd.goodsyntax
102 ; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.vasrhrnd.goodsyntax
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfmf-propagation.ll6 ; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_transfer:'
17 ; CHECK: Optimized lowered selection DAG: %bb.0 'fmf_transfer:'
31 ; CHECK-LABEL: Optimized type-legalized selection DAG: %bb.0 'fmf_setcc:'
40 ; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_setcc_canon:'
52 ; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_target_intrinsic:'
56 ; CHECK-LABEL: Legalized selection DAG: %bb.0 'fmf_target_intrinsic:'
H A Ddag-optnone.ll4 ; If fast-isel bails out to normal selection, then the DAG combiner will run,
7 ; selection patterns that depend on the legalizations and transforms that the
12 ; re-enabled in r233153 because of problems with instruction selection patterns
16 ; If instruction selection eventually becomes smart enough to run without DAG
56 ; The test case @bar is derived from an instruction selection failure case
H A Dfast-isel-abort-warm.ll10 ; CHECK: warning: Instruction selection used fallback path for foo
18 ; CHECK: warning: Instruction selection used fallback path for test_instruction_fallback
27 ; CHECK-NOT: warning: Instruction selection used fallback path for test_instruction_not_fallback
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Daddress-selection.ll24 ; MIPS-LABEL: ===== Instruction selection ends:
28 ; MIPS-XGOT-LABEL: ===== Instruction selection ends:
33 ; MM-LABEL: ===== Instruction selection ends:
37 ; MM-XGOT-LABEL: ===== Instruction selection ends:
/llvm-project-15.0.7/lld/COFF/
H A DInputFiles.cpp317 c->selection = IMAGE_COMDAT_SELECT_ASSOCIATIVE; in readAssociativeDefinition()
475 COMDATType leaderSelection = leaderChunk->selection; in handleComdatSelection()
481 selection = leaderSelection = IMAGE_COMDAT_SELECT_ANY; in handleComdatSelection()
484 if ((selection == IMAGE_COMDAT_SELECT_ANY && in handleComdatSelection()
486 (selection == IMAGE_COMDAT_SELECT_LARGEST && in handleComdatSelection()
491 leaderSelection = selection = IMAGE_COMDAT_SELECT_LARGEST; in handleComdatSelection()
512 if (selection != leaderSelection) { in handleComdatSelection()
521 switch (selection) { in handleComdatSelection()
655 COMDATType selection = (COMDATType)def->Selection; in createDefined() local
664 c->selection = selection; in createDefined()
[all …]
/llvm-project-15.0.7/mlir/test/Conversion/SPIRVToLLVM/
H A Dcontrol-flow-ops-to-llvm.mlir124 // spv.mlir.selection
130 spv.mlir.selection {
138 spv.mlir.selection {
150 spv.mlir.selection {
170 spv.mlir.selection {
194 spv.mlir.selection {
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Darm64-fallback.ll5 ; This file checks that the fallback path to selection dag works.
20 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_write_regist…
31 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointer…
47 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for strict_align_feat…
57 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for direct_mem
110 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for asm_output_ls64
121 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for asm_input_ls64
132 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for umul_s128
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/PBQP/
H A DSolution.h38 void setSelection(GraphBase::NodeId nodeId, unsigned selection) { in setSelection() argument
39 selections[nodeId] = selection; in setSelection()
/llvm-project-15.0.7/mlir/test/Conversion/SCFToSPIRV/
H A Dif.mlir13 // CHECK: spv.mlir.selection {
33 // CHECK: spv.mlir.selection {
36 // CHECK-NEXT: spv.mlir.selection {
47 // CHECK-NEXT: spv.mlir.selection {
86 // CHECK: spv.mlir.selection {
130 // CHECK: spv.mlir.selection {
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dcontrol-flow-optnone.ll4 ; to be uniform during instruction selection. The custom selection for
6 ; selection pattern to check that. That would fail, so then the branch
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Disel-const-splat-bitcast.ll3 ; The generation of a constant vector in the selection step resulted in
5 ; That bitcast was erroneously removed by the constant vector selection
6 ; function, and caused a selection error due to a type mismatch.
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dx86_64-fallback.ll4 ; This file checks that the fallback path to selection dag works.
12 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_x86_fp80_dump
21 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for ScaleObjectOverwr…
/llvm-project-15.0.7/clang/test/Sema/
H A Dnowarn-documentation-property.m7 /// It is an AND of the parent's `prefixPredicate` (e.g., the selection for
8 /// volume number) and the `filterPredicate` (selection by matching the name).
/llvm-project-15.0.7/clang/docs/
H A DRefactoringEngine.rst12 initiated using a selection in an editor or an IDE. You can combine
14 refactorings that don't lend themselves well to source selection and/or have to
75 the selection and other options passed to the refactoring action, and will pick
76 the most appropriate rule for the given selection and other options.
114 rule that simply deletes a selection, you should create a subclass of
115 ``SourceChangeRefactoringRule`` with a constructor that accepts the selection
196 The refactoring rule requirements that require some form of source selection
200 action is invoked with some sort of selection. This requirement should be
205 .. FIXME: Future selection requirements
207 .. FIXME: Maybe mention custom selection requirements?

12345678910>>...12