| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-bswap-ext.ll | 7 ; CHECK-NEXT: rev32 v0.8b, v0.8b
18 ; CHECK-NEXT: rev32 v0.8b, v0.8b
|
| H A D | aarch64-load-ext.ll | 97 ; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
141 ; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
166 ; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
213 ; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
239 ; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
285 ; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
308 ; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
370 ; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
395 ; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
396 ; CHECK-BE-NEXT: rev32 v1.8b, v1.8b
[all …]
|
| H A D | arm64-big-endian-bitconverts.ll | 332 ; CHECK: rev32 v{{[0-9]+}}.4h
347 ; CHECK: rev32 v{{[0-9]+}}.4h
360 ; CHECK: rev32 v{{[0-9]+}}.8b
424 ; CHECK: rev32 v{{[0-9]+}}.4h
437 ; CHECK: rev32 v{{[0-9]+}}.8b
489 ; CHECK: rev32 v{{[0-9]+}}.4h
502 ; CHECK: rev32 v{{[0-9]+}}.4h
586 ; CHECK: rev32 v{{[0-9]+}}.4h
601 ; CHECK: rev32 v{{[0-9]+}}.4h
683 ; CHECK: rev32 v{{[0-9]+}}.8b
[all …]
|
| H A D | bitreverse.ll | 11 ; CHECK-NEXT: rev32 v0.8b, v0.8b
116 ; CHECK-NEXT: rev32 v0.8b, v0.8b
129 ; CHECK-NEXT: rev32 v0.16b, v0.16b
|
| H A D | arm64-rev.ll | 154 ; CHECK-NEXT: rev32 x0, x8
232 ; CHECK-NEXT: rev32 x0, x0
237 ; GISEL-NEXT: rev32 x0, x0
387 ; CHECK-NEXT: rev32.8b v0, v0
393 ; GISEL-NEXT: rev32.8b v0, v0
404 ; CHECK-NEXT: rev32.4h v0, v0
410 ; GISEL-NEXT: rev32.4h v0, v0
421 ; CHECK-NEXT: rev32.16b v0, v0
440 ; CHECK-NEXT: rev32.8h v0, v0
514 ; CHECK-NEXT: rev32.8h v0, v0
[all …]
|
| H A D | neon_rbit.ll | 58 ; CHECK-NEXT: rev32 v0.8b, v0.8b
70 ; CHECK-NEXT: rev32 v0.16b, v0.16b
|
| H A D | faddp-half.ll | 146 ; CHECK-NEXT: rev32 v1.8h, v0.8h
152 ; CHECKNOFP16-NEXT: rev32 v2.8h, v0.8h
224 ; CHECKNOFP16-NEXT: rev32 v5.8h, v0.8h
226 ; CHECKNOFP16-NEXT: rev32 v4.8h, v1.8h
|
| H A D | arm64-vext_reverse.ll | 105 ; CHECK: rev32 v0.4h, v1.4h
137 ; CHECK: rev32 v0.4h, v0.4h
|
| H A D | extract-insert.ll | 79 ; BE-NEXT: rev32 v0.16b, v0.16b
|
| H A D | fp16-vector-shuffle.ll | 136 ; CHECK-NEXT: rev32 v0.4h, v0.4h
162 ; CHECK-NEXT: rev32 v0.8h, v0.8h
|
| H A D | arm64-addp.ll | 109 ; CHECK-NEXT: rev32.8h v1, v0
|
| H A D | neon-widen-shuffle.ll | 96 ; CHECK-NEXT: rev32 v0.4h, v0.4h
|
| H A D | dp1.ll | 44 ; CHECK-NEXT: rev32 x9, x9
|
| H A D | sve-fixed-length-rev.ll | 476 ; CHECK-NEXT: rev32 v0.8b, v0.8b
486 ; CHECK-NEXT: rev32 v0.16b, v0.16b
|
| H A D | highextractbitcast.ll | 213 ; CHECK-BE-NEXT: rev32 v0.4h, v0.4h
320 ; CHECK-BE-NEXT: rev32 v0.4h, v0.4h
|
| /llvm-project-15.0.7/llvm/test/MC/AArch64/ |
| H A D | neon-simd-misc.s | 23 rev32 v30.16b, v31.16b
24 rev32 v4.8h, v7.8h
25 rev32 v21.8b, v1.8b
26 rev32 v0.4h, v9.4h
|
| H A D | neon-diagnostics.s | 5183 rev32 v30.2s, v31.2s
5184 rev32 v30.4s, v31.4s
5185 rev32 v30.2d, v31.2d
|
| H A D | arm64-arithmetic-encoding.s | 442 rev32 x1, x2
|
| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ |
| H A D | bitreverse.ll | 68 define i32 @rev32(i32 %v) {
69 ; CHECK-LABEL: @rev32(
|
| /llvm-project-15.0.7/llvm/test/MC/RISCV/ |
| H A D | rv64zbp-aliases-valid.s | 83 # CHECK-S-OBJ: rev32 t0, t1
84 rev32 x5, x6 label
|
| /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/ |
| H A D | shuffle-select.ll | 25 ; CODE: rev32 v0.4h, v0.4h
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrGISel.td | 36 // Pseudo for a rev32 instruction. Produced post-legalization from
|
| /llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
| H A D | A55-neon-instructions.s | 401 rev32 v0.4h, v9.4h label
402 rev32 v21.8b, v1.8b label
403 rev32 v30.16b, v31.16b label
404 rev32 v4.8h, v7.8h label
1470 # CHECK-NEXT: 1 4 0.50 rev32 v0.4h, v9.4h
1471 # CHECK-NEXT: 1 4 0.50 rev32 v21.8b, v1.8b
1472 # CHECK-NEXT: 1 4 1.00 rev32 v30.16b, v31.16b
1473 # CHECK-NEXT: 1 4 1.00 rev32 v4.8h, v7.8h
2550 … - - - 0.50 0.50 - - - - - - rev32 v0.4h, v9.4h
2551 … - - - 0.50 0.50 - - - - - - rev32 v21.8b, v1.8b
[all …]
|
| /llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Neoverse/ |
| H A D | N2-neon-instructions.s | 401 rev32 v0.4h, v9.4h label
402 rev32 v21.8b, v1.8b label
403 rev32 v30.16b, v31.16b label
404 rev32 v4.8h, v7.8h label
1470 # CHECK-NEXT: 1 2 0.50 rev32 v0.4h, v9.4h
1471 # CHECK-NEXT: 1 2 0.50 rev32 v21.8b, v1.8b
1472 # CHECK-NEXT: 1 2 0.50 rev32 v30.16b, v31.16b
1473 # CHECK-NEXT: 1 2 0.50 rev32 v4.8h, v7.8h
2551 … - - - - - - - - - 0.50 0.50 rev32 v0.4h, v9.4h
2552 … - - - - - - - - - 0.50 0.50 rev32 v21.8b, v1.8b
[all …]
|
| /llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/ |
| H A D | arm64-arithmetic.txt | 412 # CHECK: rev32 x1, x2
|