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/llvm-project-15.0.7/llvm/test/Bitcode/
H A DbinaryIntInstructions.3.2.ll13 ; CHECK-NEXT: %res2 = add i8 %x2, %x2
14 %res2 = add i8 %x2, %x2
43 %res2 = add nuw nsw <3 x i8> %x2, %x2
63 %res2 = add nuw nsw <3 x i16> %x2, %x2
83 %res2 = add nuw nsw <3 x i32> %x2, %x2
103 %res2 = add nuw nsw <3 x i64> %x2, %x2
122 ; CHECK: %res2 = sub nuw i8 %x1, %x1
123 %res2 = sub nuw i8 %x1, %x1
147 ; CHECK-NEXT: %res2 = udiv exact i8 %x1, %x1
148 %res2 = udiv exact i8 %x1, %x1
[all …]
H A DbitwiseInstructions.3.2.ll13 ; CHECK: %res2 = shl nuw i8 %x1, %x1
14 %res2 = shl nuw i8 %x1, %x1
30 ; CHECK: %res2 = lshr exact i8 %x1, %x1
31 %res2 = lshr exact i8 %x1, %x1
41 ; CHECK-NEXT: %res2 = ashr exact i8 %x1, %x1
42 %res2 = ashr exact i8 %x1, %x1
H A DbinaryFloatInstructions.3.2.ll13 ; CHECK-NEXT: %res2 = fadd double %x2, %x2
14 %res2 = fadd double %x2, %x2
36 ; CHECK-NEXT: %res2 = fadd <3 x float> %x2, %x2
37 %res2 = fadd <3 x float> %x2, %x2
56 ; CHECK-NEXT: %res2 = fadd <3 x double> %x2, %x2
57 %res2 = fadd <3 x double> %x2, %x2
76 ; CHECK-NEXT: %res2 = fadd <3 x half> %x2, %x2
77 %res2 = fadd <3 x half> %x2, %x2
H A DaggregateInstructions.3.2.ll14 ; CHECK-NEXT: %res2 = extractvalue [4 x [4 x i8]] %x2, 1
15 %res2 = extractvalue [4 x [4 x i8 ]] %x2, 1
31 ; CHECK-NEXT: %res2 = insertvalue [4 x [4 x i8]] undef, i8 0, 0, 0
32 %res2 = insertvalue [4 x [4 x i8 ]] undef, i8 0, 0, 0
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dwmma_multiple_64.ll36 store <4 x float> %res2, <4 x float> addrspace(1)* %out2, align 16
74 store <8 x half> %res2, <8 x half> addrspace(1)* %out2, align 16
91 store <8 x half> %res2, <8 x half> addrspace(1)* %out2, align 16
110 store <8 x i16> %res2, <8 x i16> addrspace(1)* %out2, align 16
127 store <8 x i16> %res2, <8 x i16> addrspace(1)* %out2, align 16
146 store <4 x i32> %res2, <4 x i32> addrspace(1)* %out2, align 16
164 store <4 x i32> %res2, <4 x i32> addrspace(1)* %out2, align 16
181 store <4 x i32> %res2, <4 x i32> addrspace(1)* %out2, align 16
198 store <4 x i32> %res2, <4 x i32> addrspace(1)* %out2, align 16
215 store <4 x i32> %res2, <4 x i32> addrspace(1)* %out2, align 16
[all …]
H A Ddivergence-driven-abs.ll10 %res2 = add i32 %res, 2
11 store i32 %res2, i32 addrspace(1)* %out, align 4
26 %res2 = add i32 %res, 2
27 store i32 %res2, i32 addrspace(1)* %out, align 4
42 %res2 = add <2 x i32> %res, %t1
43 store <2 x i32> %res2, <2 x i32> addrspace(1)* %out, align 4
63 %res2 = add <2 x i32> %res, %t1
64 store <2 x i32> %res2, <2 x i32> addrspace(1)* %out, align 4
H A Dwmma_multiple_32.ll40 store <8 x float> %res2, <8 x float> addrspace(1)* %out2, align 32
130 store <16 x i16> %res2, <16 x i16> addrspace(1)* %out2, align 32
174 store <8 x i32> %res2, <8 x i32> addrspace(1)* %out2, align 32
195 store <8 x i32> %res2, <8 x i32> addrspace(1)* %out2, align 32
216 store <8 x i32> %res2, <8 x i32> addrspace(1)* %out2, align 32
237 store <8 x i32> %res2, <8 x i32> addrspace(1)* %out2, align 32
258 store <8 x i32> %res2, <8 x i32> addrspace(1)* %out2, align 32
279 store <8 x i32> %res2, <8 x i32> addrspace(1)* %out2, align 32
300 store <8 x i32> %res2, <8 x i32> addrspace(1)* %out2, align 32
321 store <8 x i32> %res2, <8 x i32> addrspace(1)* %out2, align 32
[all …]
/llvm-project-15.0.7/libcxx/test/std/algorithms/algorithms.results/
H A Dmin_max_result.pass.cpp68 std::ranges::min_max_result<ConvertibleFrom<int>> res2 = res; in test() local
69 assert(res2.min.content == 10); in test()
70 assert(res2.max.content == 1); in test()
76 auto res2 = std::move(res); in test() local
79 assert(res2.min.get() == 1); in test()
80 assert(res2.max.get() == 1); in test()
H A Din_found_result.pass.cpp72 std::ranges::in_found_result<ConvertibleFrom<int>> res2 = res; in test() local
73 assert(res2.in.content == 10); in test()
74 assert(res2.found == true); in test()
80 auto res2 = std::move(res); in test() local
81 assert(res2.in.get() == 1); in test()
82 assert(!res2.found); in test()
H A Din_out_result.pass.cpp67 std::ranges::in_out_result<ConvertibleFrom<double>, ConvertibleFrom<int>> res2 = res; in test() local
68 assert(res2.in.content == 10); in test()
69 assert(res2.out.content == 1); in test()
75 auto res2 = std::move(res); in test() local
78 assert(res2.in.get() == 1); in test()
79 assert(res2.out == 10); in test()
H A Din_fun_result.pass.cpp72 std::ranges::in_fun_result<ConvertibleFrom<int>, ConvertibleFrom<double>> res2 = res; in test() local
73 assert(res2.in.content == 10); in test()
74 assert(res2.fun.content == 0.); in test()
80 auto res2 = static_cast<std::ranges::in_fun_result<MoveOnly, int>>(std::move(res)); in test() local
82 assert(res2.in.get() == 1); in test()
83 assert(res2.fun == 2); in test()
H A Din_in_out_result.pass.cpp76 …in_in_out_result<ConvertibleFrom<int>, ConvertibleFrom<double>, ConvertibleFrom<float>> res2 = res; in test() local
77 assert(res2.in1.content == 10); in test()
78 assert(res2.in2.content == 0.); in test()
79 assert(res2.out.content == 1.f); in test()
84 auto res2 = static_cast<std::ranges::in_in_out_result<MoveOnly, int, int>>(std::move(res1)); in test() local
86 assert(res2.in1.get() == 1); in test()
H A Din_out_out_result.pass.cpp74 …n_out_out_result<ConvertibleFrom<int>, ConvertibleFrom<double>, ConvertibleFrom<float>> res2 = res; in test() local
75 assert(res2.in.content == 10); in test()
76 assert(res2.out1.content == 0.); in test()
77 assert(res2.out2.content == 1.f); in test()
82 auto res2 = static_cast<std::ranges::in_out_out_result<MoveOnly, int, int>>(std::move(res1)); in test() local
84 assert(res2.in.get() == 1); in test()
/llvm-project-15.0.7/llvm/test/Transforms/ConstantHoisting/ARM/
H A Dbad-cases.ll54 ; CHECK: %res2 = srem i32 %l2, 1000000000
60 %l2 = phi i32 [%res2, %loop], [%in2, %entry]
63 %res2 = srem i32 %l2, 1000000000
64 store volatile i32 %res2, i32* %addr
65 %again = icmp eq i32 %res1, %res2
75 ; CHECK: %res2 = urem i32 %l2, 1000000000
82 %l2 = phi i32 [%res2, %loop], [%in2, %entry]
85 %res2 = urem i32 %l2, 1000000000
86 store volatile i32 %res2, i32* %addr
87 %again = icmp eq i32 %res1, %res2
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dasm-18.ll376 %or2 = or i32 %res2, 34661
397 %or2 = or i32 %res2, 34661
418 %xor2 = xor i32 %res2, 34661
439 %xor2 = xor i32 %res2, 34661
460 %and2 = and i32 %res2, -8000
506 ret i32 %res2
531 ret i32 %res2
560 ret i32 %res2
577 %add2 = add i32 %res2, 1
598 %add2 = add i32 %res2, 1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Davx512-intrinsics-x86_64.ll34 %res2 = add i64 %res0, %res1
35 ret i64 %res2
48 %res2 = add i64 %res0, %res1
49 ret i64 %res2
84 %res2 = add i64 %res0, %res1
85 ret i64 %res2
98 %res2 = add i32 %res0, %res1
99 ret i32 %res2
112 %res2 = add i64 %res0, %res1
113 ret i64 %res2
[all …]
H A Dvpshufbitqbm-intrinsics-upgrade.ll14 %res2 = call i16 @llvm.x86.avx512.mask.vpshufbitqmb.128(<16 x i8> %c, <16 x i8> %d, i16 %res)
15 ret i16 %res2
28 %res2 = call i32 @llvm.x86.avx512.mask.vpshufbitqmb.256(<32 x i8> %c, <32 x i8> %d, i32 %res)
29 ret i32 %res2
42 %res2 = call i64 @llvm.x86.avx512.mask.vpshufbitqmb.512(<64 x i8> %c, <64 x i8> %d, i64 %res)
43 ret i64 %res2
/llvm-project-15.0.7/compiler-rt/test/sanitizer_common/TestCases/Posix/
H A Dreadlink.c20 ssize_t res2 = readlink(symlink_path, readlink_path, sizeof(readlink_path)); in main() local
21 assert(res2 >= 0); in main()
22 readlink_path[res2] = '\0'; in main()
H A Dreadlinkat.c21 int res2 = readlinkat(AT_FDCWD, symlink_path, readlinkat_path, in main() local
23 assert(res2 >= 0); in main()
24 readlinkat_path[res2] = '\0'; in main()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-raddhn-combine.ll13 %res2 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %y, i32 8)
14 …%shuffle = shufflevector <8 x i8> %res, <8 x i8> %res2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i3…
27 %res2 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %y, i32 16)
28 …%shuffle = shufflevector <4 x i16> %res, <4 x i16> %res2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i…
41 %res2 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %y, i32 32)
42 %shuffle = shufflevector <2 x i32> %res, <2 x i32> %res2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
/llvm-project-15.0.7/llvm/test/Transforms/ConstantHoisting/X86/
H A Dbad-cases.ll28 %l2 = phi i64 [%res2, %loop], [%in2, %entry]
31 %res2 = srem i64 %l2, 4294967296
32 store volatile i64 %res2, i64* %addr
33 %again = icmp eq i64 %res1, %res2
62 %l2 = phi i64 [%res2, %loop], [%in2, %entry]
65 %res2 = urem i64 %l2, 4294967296
66 store volatile i64 %res2, i64* %addr
67 %again = icmp eq i64 %res1, %res2
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfold-rlwinm-1.ll6 @res2 = dso_local local_unnamed_addr global i32 0, align 4
29 ; CHECK-NEXT: addis r4, r2, res2@toc@ha
34 ; CHECK-NEXT: stw r5, res2@toc@l(r4)
40 store i32 %conv, i32* @res2, align 4
/llvm-project-15.0.7/flang/test/Lower/
H A Dstatement-function.f9042 real :: res1, res2 local
65 res2 = func2(x)
70 test_stmt_1 = res1 + res2
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Docteon.ll41 %res2 = zext i1 %res to i64
42 ret i64 %res2
57 %res2 = zext i1 %res to i64
58 ret i64 %res2
72 %res2 = zext i1 %res to i64
73 ret i64 %res2
88 %res2 = zext i1 %res to i64
89 ret i64 %res2
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/
H A Dlogic-miscext3.ll15 ; Z13: Cost Model: Found an estimated cost of 1 for instruction: %res2 = xor i32 %c2, -1
16 ; Z15: Cost Model: Found an estimated cost of 0 for instruction: %res2 = xor i32 %c2, -1
37 %res2 = xor i32 %c2, -1
38 store i32 %res2, i32* undef
62 ; Z13: Cost Model: Found an estimated cost of 1 for instruction: %res2 = xor i64 %c2, -1
63 ; Z15: Cost Model: Found an estimated cost of 0 for instruction: %res2 = xor i64 %c2, -1
83 %res2 = xor i64 %c2, -1
84 store i64 %res2, i64* undef

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