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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmem-builtins.ll14 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, memcmp@rel32@lo+4
15 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, memcmp@rel32@hi+12
25 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, memchr@rel32@lo+4
26 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, memchr@rel32@hi+12
35 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcpy@rel32@lo+4
36 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcpy@rel32@hi+12
45 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcmp@rel32@lo+4
46 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcmp@rel32@hi+12
55 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strlen@rel32@lo+4
56 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, strlen@rel32@hi+12
[all …]
H A Dcall-reqd-group-size.ll21 ; CHECK-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
22 ; CHECK-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
40 ; CHECK-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
41 ; CHECK-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
59 ; CHECK-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
60 ; CHECK-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
78 ; CHECK-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
79 ; CHECK-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
97 ; CHECK-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
98 ; CHECK-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
[all …]
H A Dcall-constexpr.ll5 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ret_i32_noinline@rel32@lo+4
6 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ret_i32_noinline@rel32@hi+12
26 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@lo+4
27 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@hi+12
38 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@lo+4
39 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@hi+12
62 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, use_workitem_id_x@rel32@lo+4
63 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, use_workitem_id_x@rel32@hi+12
76 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@lo+4
77 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@hi+12
H A Dmachine-cse-commute-target-flags.mir74 …ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @func, implici…
77 %1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @func, implicit-def dead $scc
78 %2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @func, %0.sub0, implicit-def dead $scc
94 …ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @gv + 4, impli…
97 %1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc
98 %2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 4, %0.sub0, implicit-def dead $scc
114 …ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @gv + 4, impli…
115 …; CHECK-NEXT: [[S_ADD_U32_1:%[0-9]+]]:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 8, […
118 %1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc
119 %2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 8, %0.sub0, implicit-def dead $scc
H A Dcc-update.ll85 ; GFX803-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4
86 ; GFX803-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12
104 ; GFX900-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4
105 ; GFX900-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12
125 ; GFX1010-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4
142 ; GFX1100-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4
172 ; GFX803-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4
194 ; GFX900-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4
218 ; GFX1010-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4
339 ; GFX803-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4
[all …]
H A Dvirtregrewrite-undef-identity-copy.mir33 …gpr6_sgpr7 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel3…
38 …gpr6_sgpr7 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @bar + 4, target-flags(amdgpu-rel3…
50 …%2:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel3…
55 …%3:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @bar + 4, target-flags(amdgpu-rel3…
H A Dasm-printer-check-vcc.mir5 # GCN: s_add_u32 vcc_lo, vcc_lo, bar@rel32@lo+4
6 # GCN: s_addc_u32 vcc_hi, vcc_hi, bar@rel32@hi+12
21 … $vcc_lo = S_ADD_U32 internal $vcc_lo, target-flags(amdgpu-rel32-lo) @bar + 4, implicit-def $scc
22 …$vcc_hi = S_ADDC_U32 internal $vcc_hi, target-flags(amdgpu-rel32-hi) @bar + 12, implicit-def $scc,…
H A Dgfx-callable-argument-types.ll110 ; GFX9-NEXT: s_add_u32 s34, s34, external_void_func_i1@rel32@lo+4
111 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_i1@rel32@hi+12
137 ; GFX10-NEXT: s_add_u32 s34, s34, external_void_func_i1@rel32@lo+4
138 ; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_i1@rel32@hi+12
166 ; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_i1@rel32@lo+4
167 ; GFX11-NEXT: s_addc_u32 s1, s1, external_void_func_i1@rel32@hi+12
486 ; GFX9-NEXT: s_add_u32 s34, s34, external_void_func_i8@rel32@lo+4
512 ; GFX10-NEXT: s_add_u32 s34, s34, external_void_func_i8@rel32@lo+4
540 ; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_i8@rel32@lo+4
541 ; GFX11-NEXT: s_addc_u32 s1, s1, external_void_func_i8@rel32@hi+12
[all …]
H A Dneed-fp-from-vgpr-spills.ll40 ; CHECK-NEXT: s_add_u32 s4, s4, callee_has_fp@rel32@lo+4
41 ; CHECK-NEXT: s_addc_u32 s5, s5, callee_has_fp@rel32@hi+12
75 ; CHECK-NEXT: s_add_u32 s4, s4, csr_vgpr_spill_fp_callee@rel32@lo+4
76 ; CHECK-NEXT: s_addc_u32 s5, s5, csr_vgpr_spill_fp_callee@rel32@hi+12
102 ; CHECK-NEXT: s_add_u32 s4, s4, callee_has_fp@rel32@lo+4
103 ; CHECK-NEXT: s_addc_u32 s5, s5, callee_has_fp@rel32@hi+12
125 ; CHECK-NEXT: s_add_u32 s4, s4, csr_vgpr_spill_fp_tailcall_callee@rel32@lo+4
164 ; CHECK-NEXT: s_add_u32 s4, s4, tail_call@rel32@lo+4
165 ; CHECK-NEXT: s_addc_u32 s5, s5, tail_call@rel32@hi+12
228 ; CHECK-NEXT: s_add_u32 s4, s4, caller_save_vgpr_spill_fp@rel32@lo+4
[all …]
H A Dcall-waitcnt.ll19 ; GCN-NEXT: s_add_u32 s8, s8, func@rel32@lo+4
20 ; GCN-NEXT: s_addc_u32 s9, s9, func@rel32@hi+12
44 ; GCN-NEXT: s_add_u32 s8, s8, func@rel32@lo+4
45 ; GCN-NEXT: s_addc_u32 s9, s9, func@rel32@hi+12
66 ; GCN-NEXT: s_add_u32 s8, s8, func@rel32@lo+4
67 ; GCN-NEXT: s_addc_u32 s9, s9, func@rel32@hi+12
89 ; GCN-NEXT: s_add_u32 s8, s8, func.return@rel32@lo+4
90 ; GCN-NEXT: s_addc_u32 s9, s9, func.return@rel32@hi+12
145 ; GCN-NEXT: s_add_u32 s4, s4, func@rel32@lo+4
146 ; GCN-NEXT: s_addc_u32 s5, s5, func@rel32@hi+12
H A Dgfx-callable-preserved-registers.ll23 ; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4
24 ; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12
55 ; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4
56 ; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12
89 ; GFX11-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4
90 ; GFX11-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12
228 ; GFX9-NEXT: s_add_u32 s34, s34, external_void_func_void@rel32@lo+4
295 ; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_void@rel32@lo+4
343 ; GFX9-NEXT: s_add_u32 s34, s34, external_void_func_void@rel32@lo+4
416 ; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_void@rel32@lo+4
[all …]
H A Dfunction-call-relocs.ll22 ; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], protected_func@rel32@lo+4
23 ; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], protected_func@rel32@hi+12
32 ; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], hidden_func@rel32@lo+4
33 ; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], hidden_func@rel32@hi+12
H A Dcall-preserved-registers.ll145 ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void@rel32@lo+4
146 ; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void@rel32@hi+12
149 ; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4
150 ; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12
174 ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void@rel32@lo+4
175 ; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void@rel32@hi+12
177 ; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4
178 ; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12
207 ; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4
208 ; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12
[all …]
H A Dcross-block-use-is-not-abi-copy.ll39 ; GCN-NEXT: s_add_u32 s16, s16, func_v2f32@rel32@lo+4
40 ; GCN-NEXT: s_addc_u32 s17, s17, func_v2f32@rel32@hi+12
73 ; GCN-NEXT: s_add_u32 s16, s16, func_v3f32@rel32@lo+4
74 ; GCN-NEXT: s_addc_u32 s17, s17, func_v3f32@rel32@hi+12
107 ; GCN-NEXT: s_add_u32 s16, s16, func_v4f16@rel32@lo+4
108 ; GCN-NEXT: s_addc_u32 s17, s17, func_v4f16@rel32@hi+12
141 ; GCN-NEXT: s_add_u32 s16, s16, func_struct@rel32@lo+4
142 ; GCN-NEXT: s_addc_u32 s17, s17, func_struct@rel32@hi+12
192 ; GCN-NEXT: s_add_u32 s18, s18, func_v3i16@rel32@lo+4
193 ; GCN-NEXT: s_addc_u32 s19, s19, func_v3i16@rel32@hi+12
[all …]
H A Dcall-waw-waitcnt.mir35 …; GCN-NEXT: $sgpr4 = S_ADD_U32 internal $sgpr4, target-flags(amdgpu-rel32-lo) @func + 4, implici…
36 …; GCN-NEXT: $sgpr5 = S_ADDC_U32 internal $sgpr5, target-flags(amdgpu-rel32-hi) @func + 4, implic…
48 $sgpr4 = S_ADD_U32 internal $sgpr4, target-flags(amdgpu-rel32-lo) @func + 4, implicit-def $scc
49 …$sgpr5 = S_ADDC_U32 internal $sgpr5, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def $scc, i…
H A Dglobal-constant.ll15 ; GCN: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4
16 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1@rel32@hi+12
18 ; GCN: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4
19 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2@rel32@hi+12
H A Dstack-pointer-offset-relative-frameindex.ll26 ; MUBUF-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+4
27 ; MUBUF-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+12
62 ; FLATSCR-NEXT: s_add_u32 s0, s0, svm_eval_nodes@rel32@lo+4
63 ; FLATSCR-NEXT: s_addc_u32 s1, s1, svm_eval_nodes@rel32@hi+12
89 ; MUBUF11-NEXT: s_add_u32 s0, s0, svm_eval_nodes@rel32@lo+4
90 ; MUBUF11-NEXT: s_addc_u32 s1, s1, svm_eval_nodes@rel32@hi+12
117 ; FLATSCR11-NEXT: s_add_u32 s0, s0, svm_eval_nodes@rel32@lo+4
118 ; FLATSCR11-NEXT: s_addc_u32 s1, s1, svm_eval_nodes@rel32@hi+12
H A Drel32.ll9 ; CHECK-NEXT: s_add_u32 s[[LO]], s[[LO]], g@rel32@lo-4
10 ; CHECK-NEXT: s_addc_u32 s[[HI]], s[[HI]], g@rel32@hi+4
H A Dcall-argument-types.ll68 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1@rel32@lo+4
69 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1@rel32@hi+12
88 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_signext@rel32@lo+4
123 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8@rel32@lo+4
124 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8@rel32@hi+12
141 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_signext@rel32@lo+4
159 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_zeroext@rel32@lo+4
222 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i32@rel32@lo+4
223 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i32@rel32@hi+12
238 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i64@rel32@lo+4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/AMDGPU/
H A Dtarget-flags.mir25 …]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel3…
28 …%0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @f…
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dglobal-value.ll55 …p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant + 4, target-flags(amdg…
66 …(p1) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_global + 4, target-flags(amdgp…
77 …999) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_other + 4, target-flags(amdgpu…
99 …4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32 + 4, target-flags(amd…
H A Dassert-align.ll21 ; CHECK-NEXT: s_add_u32 s16, s16, ext@rel32@lo+4
22 ; CHECK-NEXT: s_addc_u32 s17, s17, ext@rel32@hi+12
49 ; CHECK-NEXT: s_add_u32 s16, s16, ext@rel32@lo+4
50 ; CHECK-NEXT: s_addc_u32 s17, s17, ext@rel32@hi+12
H A Dcall-outgoing-stack-args.ll28 ; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_v16i32_v16i32_v4i32@rel32@lo+4
29 ; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_v16i32_v16i32_v4i32@rel32@hi+12
47 ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_v16i32_v16i32_v4i32@rel32@lo+4
115 ; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_byval@rel32@lo+4
116 ; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_byval@rel32@hi+12
208 ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_byval@rel32@lo+4
209 ; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_byval@rel32@hi+12
320 ; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_byval@rel32@lo+4
321 ; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_byval@rel32@hi+12
399 ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_byval@rel32@lo+4
[all …]
H A Dlocalizer.ll185 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv2@rel32@lo+4
186 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv2@rel32@hi+12
191 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv3@rel32@lo+4
192 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv3@rel32@hi+12
200 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv0@rel32@lo+4
201 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv0@rel32@hi+12
206 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv1@rel32@lo+4
207 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv1@rel32@hi+12
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dreloc.s27 s_mov_b32 s5, global_var3@rel32@lo
28 s_mov_b32 s6, global_var4@rel32@hi

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