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Searched refs:reglist (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp512 Op->RegList.List1From = reglist[i]; in createRegList()
515 Op->RegList.List2From = reglist[i]; in createRegList()
518 Op->RegList.List3From = reglist[i]; in createRegList()
521 Op->RegList.List4From = reglist[i]; in createRegList()
1519 SmallVector<unsigned, 4> reglist; in parseRegList() local
1542 reglist.push_back(Ry); in parseRegList()
1543 reglist.push_back(Rz); in parseRegList()
1551 reglist.push_back(Ry); in parseRegList()
1552 reglist.push_back(Ry); in parseRegList()
1556 reglist.push_back(Ry); in parseRegList()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrThumb.td826 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
841 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
844 let InOperandList = (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops);
854 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
867 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
872 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
882 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1741 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1743 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
H A DARMInstrThumb2.td1975 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3857 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
5086 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
5088 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
5092 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
5094 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
5098 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
5100 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
5104 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
5106 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
[all …]
H A DARMInstrInfo.td590 def reglist : Operand<i32> {
3453 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3462 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3473 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3482 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3493 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3502 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3513 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3522 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3554 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td524 def reglist : Operand<i32> {
546 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
553 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
889 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
893 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td389 (ins reglist:$regs, variable_ops), "push16 $regs", []> {
401 (ins reglist:$regs, variable_ops), "pop16 $regs", []> {
H A DCSKYInstrInfo.td398 def reglist : Operand<iPTR> {
832 def PUSH32 : I_12_PP<0b11111, 0b00000, (outs), (ins reglist:$regs, variable_ops), "push32 $regs">;
835 def POP32 : I_12_PP<0b11110, 0b00000, (outs), (ins reglist:$regs, variable_ops), "pop32 $regs">;
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2457 unsigned reglist = fieldFromInstruction(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction() local
2535 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) in DecodeMemMultipleWritebackInstruction()
6448 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | in DecodeVSCCLRM() local
6451 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { in DecodeVSCCLRM()
6455 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | in DecodeVSCCLRM() local
6458 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { in DecodeVSCCLRM()