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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Drbit.ll7 ; CHECK: rbit w0, w0
10 %rbit.i = call i32 @llvm.aarch64.rbit.i32(i32 %t)
11 ret i32 %rbit.i
15 ; CHECK: rbit x0, x0
18 %rbit.i = call i64 @llvm.aarch64.rbit.i64(i64 %t)
19 ret i64 %rbit.i
22 declare i64 @llvm.aarch64.rbit.i64(i64)
26 ; CHECK: rbit w0, w0
30 ret i32 %rbit
34 ; CHECK: rbit x0, x0
[all …]
H A Dneon_rbit.ll7 declare <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8>) nounwind readnone
12 ; CHECK-NEXT: rbit v0.8b, v0.8b
14 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %A)
23 ; CHECK-NEXT: rbit v0.16b, v0.16b
35 ; CHECK-NEXT: rbit v0.8b, v0.8b
47 ; CHECK-NEXT: rbit v0.16b, v0.16b
49 %tmp3 = call <8 x i16> @llvm.aarch64.neon.rbit.v8i16(<8 x i16> %A)
59 ; CHECK-NEXT: rbit v0.8b, v0.8b
71 ; CHECK-NEXT: rbit v0.16b, v0.16b
83 ; CHECK-NEXT: rbit v0.8b, v0.8b
[all …]
H A Dbitreverse.ll12 ; CHECK-NEXT: rbit v0.8b, v0.8b
24 ; CHECK-NEXT: rbit w8, w0
36 ; CHECK-NEXT: rbit w8, w0
48 ; CHECK-NEXT: rbit w0, w0
59 ; CHECK-NEXT: rbit x0, x0
70 ; CHECK-NEXT: rbit v0.8b, v0.8b
81 ; CHECK-NEXT: rbit v0.16b, v0.16b
93 ; CHECK-NEXT: rbit v0.8b, v0.8b
105 ; CHECK-NEXT: rbit v0.16b, v0.16b
117 ; CHECK-NEXT: rbit v0.8b, v0.8b
[all …]
H A Dfold-csel-cttz-and.ll12 ; CHECK-NEXT: rbit w8, w0
26 ; CHECK-NEXT: rbit x8, x0
40 ; CHECK-NEXT: rbit w8, w0
54 ; CHECK-NEXT: rbit x8, x0
68 ; CHECK-NEXT: rbit x8, x0
84 ; CHECK-NEXT: rbit w8, w0
99 ; CHECK-NEXT: rbit w8, w0
114 ; CHECK-NEXT: rbit w9, w0
144 ; CHECK-NEXT: rbit w8, w0
H A Dsve-intrinsics-reversal.ll12 ; CHECK-NEXT: rbit z0.b, p0/m, z1.b
14 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> %a,
23 ; CHECK-NEXT: rbit z0.h, p0/m, z1.h
25 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> %a,
34 ; CHECK-NEXT: rbit z0.s, p0/m, z1.s
36 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> %a,
45 ; CHECK-NEXT: rbit z0.d, p0/m, z1.d
47 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> %a,
132 declare <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <v…
133 declare <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <v…
[all …]
H A Dsve-fixed-length-rev.ll17 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
29 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
41 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
81 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
95 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
109 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
121 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
133 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
173 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
187 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
[all …]
H A Dsve-rev.ll14 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
24 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
34 ; CHECK-NEXT: rbit z0.s, p0/m, z0.s
44 ; CHECK-NEXT: rbit z0.d, p0/m, z0.d
H A Dsve-fixed-length-bit-counting.ll745 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
757 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
769 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
813 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
828 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
843 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
855 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
867 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
911 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
926 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
[all …]
H A Dsve-bit-counting.ll110 ; CHECK-NEXT: rbit z0.b, p0/m, z0.b
122 ; CHECK-NEXT: rbit z0.h, p0/m, z0.h
134 ; CHECK-NEXT: rbit z0.s, p0/m, z0.s
146 ; CHECK-NEXT: rbit z0.d, p0/m, z0.d
H A Darm64-vbitwise.ll5 ;CHECK: rbit.8b
13 ;CHECK: rbit.16b
H A Ddp1.ll141 ; CHECK-NEXT: rbit w9, w9
157 ; CHECK-NEXT: rbit x9, x9
173 ; CHECK-NEXT: rbit w9, w9
189 ; CHECK-NEXT: rbit x9, x9
H A Dneon-vmull-high-p64.ll71 %vrbit.i = call <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8> %8) #0
92 declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) #0
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Drbit.ll3 ; CHECK-LABEL: rbit
4 ; CHECK: rbit r0, r0
5 define i32 @rbit(i32 %t) {
7 %rbit = call i32 @llvm.arm.rbit(i32 %t)
8 ret i32 %rbit
13 ; CHECK-NOT: rbit
17 %rbit.i = call i32 @llvm.arm.rbit(i32 0)
18 ret i32 %rbit.i
21 declare i32 @llvm.arm.rbit(i32)
26 ; CHECK: rbit r0, r0
[all …]
H A Dbit-reverse-to-rbit.ll8 ;CHECK-NOT: rbit
9 ;RBIT: rbit
H A Dcttz.ll19 ; CHECK-NEXT: rbit r0, r0
68 ; CHECK-NEXT: rbit r0, r0
116 ; CHECK-NEXT: rbit r0, r0
164 ; CHECK-NEXT: rbit r1, r1
165 ; CHECK-NEXT: rbit r2, r0
238 ; CHECK-NEXT: rbit r0, r0
280 ; CHECK-NEXT: rbit r0, r0
323 ; CHECK-NEXT: rbit r0, r0
365 ; CHECK-NEXT: rbit r1, r1
366 ; CHECK-NEXT: rbit r2, r0
H A Dcttz_vector.ll31 ; CHECK-NEXT: rbit r1, r1
124 ; CHECK-NEXT: rbit r1, r1
194 ; CHECK-NEXT: rbit r1, r1
290 ; CHECK-NEXT: rbit r1, r1
379 ; CHECK-NEXT: rbit r1, r1
446 ; CHECK-NEXT: rbit r1, r1
/llvm-project-15.0.7/llvm/test/MC/AArch64/SVE/
H A Drbit.s12 rbit z0.b, p7/m, z31.b label
18 rbit z0.h, p7/m, z31.h label
24 rbit z0.s, p7/m, z31.s label
30 rbit z0.d, p7/m, z31.d label
46 rbit z0.d, p7/m, z31.d label
58 rbit z0.d, p7/m, z31.d label
H A Drbit-diagnostics.s7 rbit z0.d, p8/m, z0.d label
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-cttz.ll8 ; CHECK-NEXT: rbit r1, r1
9 ; CHECK-NEXT: rbit r2, r0
19 ; CHECK-NEXT: rbit r1, r1
20 ; CHECK-NEXT: rbit r2, r0
77 ; CHECK-NEXT: rbit r1, r1
78 ; CHECK-NEXT: rbit r2, r0
88 ; CHECK-NEXT: rbit r1, r1
89 ; CHECK-NEXT: rbit r2, r0
H A Dmve-pred-bitcast.ll31 ; CHECK-BE-NEXT: rbit r0, r0
94 ; CHECK-BE-NEXT: rbit r0, r0
146 ; CHECK-BE-NEXT: rbit r0, r0
185 ; CHECK-BE-NEXT: rbit r0, r0
353 ; CHECK-BE-NEXT: rbit r0, r0
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dnot-armv4.s8 rbit r4,r9 label
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dbuiltins-arm64.c17 unsigned rbit(unsigned a) { in rbit() function
H A Dbuiltins-arm.c88 unsigned rbit(unsigned a) { in rbit() function
/llvm-project-15.0.7/libc/AOR_v20.02/string/aarch64/
H A Dstrchr-mte.S120 rbit tmp1, tmp1
H A Dstrchrnul.S109 rbit tmp1, tmp1

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