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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dv_cvt_pk_u8_f32.ll4 declare i32 @llvm.amdgcn.cvt.pk.u8.f32(float, i32, i32) #0
9 %result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 0, i32 %reg) #0
17 %result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 1, i32 %reg) #0
25 %result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 2, i32 %reg) #0
33 %result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 3, i32 %reg) #0
44 %result0 = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 0, i32 %reg) #0
45 %result1 = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 1, i32 %result0) #0
46 %result2 = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 2, i32 %result1) #0
47 %result3 = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 3, i32 %result2) #0
55 %result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 %idx, i32 %reg) #0
H A Dllvm.amdgcn.cvt.fp8.ll5 declare <2 x float> @llvm.amdgcn.cvt.pk.f32.bf8(i32, i1)
6 declare <2 x float> @llvm.amdgcn.cvt.pk.f32.fp8(i32, i1)
7 declare i32 @llvm.amdgcn.cvt.pk.bf8.f32(float, float, i32, i1)
8 declare i32 @llvm.amdgcn.cvt.pk.fp8.f32(float, float, i32, i1)
71 %ret = tail call <2 x float> @llvm.amdgcn.cvt.pk.f32.bf8(i32 %a, i1 false)
78 %ret = tail call <2 x float> @llvm.amdgcn.cvt.pk.f32.bf8(i32 %a, i1 true)
85 %ret = tail call <2 x float> @llvm.amdgcn.cvt.pk.f32.fp8(i32 %a, i1 false)
92 %ret = tail call <2 x float> @llvm.amdgcn.cvt.pk.f32.fp8(i32 %a, i1 true)
100 %ret = tail call i32 @llvm.amdgcn.cvt.pk.bf8.f32(float %x, float %y, i32 %old, i1 false)
108 %ret = tail call i32 @llvm.amdgcn.cvt.pk.bf8.f32(float %x, float %y, i32 %old, i1 true)
[all …]
H A Dllvm.amdgcn.cvt.pk.i16.ll12 %result = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 %y)
22 %result = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 %x)
41 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %a, i32 %b)
56 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %a, i32 1)
72 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 1, i32 %a)
78 declare <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32, i32) #1
H A Dllvm.amdgcn.cvt.pk.u16.ll12 %result = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 %y)
22 %result = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 %x)
41 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %a, i32 %b)
56 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %a, i32 1)
72 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 1, i32 %a)
78 declare <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32, i32) #1
H A Dllvm.amdgcn.qsad.pk.u16.u8.ll4 declare i64 @llvm.amdgcn.qsad.pk.u16.u8(i64, i32, i64) #0
12 %tmp1 = call i64 @llvm.amdgcn.qsad.pk.u16.u8(i64 %tmp, i32 100, i64 100) #0
26 %tmp3 = call i64 @llvm.amdgcn.qsad.pk.u16.u8(i64 %tmp, i32 %tmp1, i64 %tmp2) #0
H A Dllvm.amdgcn.mqsad.pk.u16.u8.ll4 declare i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64, i32, i64) #0
12 %tmp1 = call i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64 %tmp, i32 100, i64 100) #0
26 %tmp3 = call i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64 %tmp, i32 %tmp1, i64 %tmp2) #0
H A Dsgpr-copy-local-cse.ll22 %pk = getelementptr float, float addrspace(1)* %p, i32 %k
23 store float %sum, float addrspace(1)* %pk
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dbuiltins-amdgcn-fp8.cl21 // CHECK-GFX940: call <2 x float> @llvm.amdgcn.cvt.pk.f32.bf8(i32 %a, i1 false)
28 // CHECK-GFX940: call <2 x float> @llvm.amdgcn.cvt.pk.f32.fp8(i32 %a, i1 true)
35 // CHECK-GFX940: call i32 @llvm.amdgcn.cvt.pk.bf8.f32(float %a, float %b, i32 %old, i1 false)
42 // CHECK-GFX940: call i32 @llvm.amdgcn.cvt.pk.fp8.f32(float %a, float %b, i32 %old, i1 true)
H A Dbuiltins-amdgcn.cl706 // CHECK: tail call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %src0, i32 %src1)
712 // CHECK: tail call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %src0, i32 %src1)
718 // CHECK: tail call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src0, i32 %src1, i32 %src2)
748 // CHECK: call i64 @llvm.amdgcn.qsad.pk.u16.u8(i64 %src0, i32 %src1, i64 %src2)
754 // CHECK: call i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64 %src0, i32 %src1, i64 %src2)
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinst-select-amdgcn.cvt.pk.i16.mir23 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1
46 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1
68 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1
H A Dinst-select-amdgcn.cvt.pk.u16.mir23 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1
46 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1
68 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1
/llvm-project-15.0.7/clang/test/Analysis/
H A Dmisc-ps.c100 int *pk = bazR10376675(); in barR10376675() local
101 pm = pk; //expected-warning {{never read}} in barR10376675()
/llvm-project-15.0.7/openmp/runtime/test/tasking/
H A Dkmp_task_reduction_nest.cpp115 void calc_serial(int *pi, long long *pj, double *px, long long *pk, double *py) in calc_serial() argument
126 *pk -= l; in calc_serial()
134 *pk -= l; in calc_serial()
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td2362 // llvm.amdgcn.cvt.pk.f32.bf8 float2 vdst, int srcA, imm word_sel
2369 // llvm.amdgcn.cvt.pk.f32.fp8 float2 vdst, int srcA, imm word_sel.
2375 // llvm.amdgcn.cvt.pk.bf8.f32 int vdst, float srcA, float srcB, int old, imm word_sel
2382 // llvm.amdgcn.cvt.pk.fp8.f32 int vdst, float srcA, float srcB, int old, imm word_sel
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td594 def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
617 : SubtargetFeature<"atomic-pk-fadd-no-rtn-insts",
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Damdgcn-intrinsics.ll970 ; llvm.amdgcn.cvt.pk.i16
973 declare <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32, i32) nounwind readnone
977 ; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 undef, i32 [[Y:%.*]])
980 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 undef, i32 %y)
989 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 undef)
997 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 undef, i32 undef)
1002 ; llvm.amdgcn.cvt.pk.u16
1005 declare <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32, i32) nounwind readnone
1012 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 undef, i32 %y)
1021 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 undef)
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/llvm-project-15.0.7/lldb/test/API/functionalities/postmortem/FreeBSDKernel/
H A Dvmcore-amd64-minidump.bz21minidump FreeBSD/