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/llvm-project-15.0.7/llvm/test/MC/AArch64/SVE/
H A Dorr.s14 orr z5.b, z5.b, #0xf9 label
20 orr z23.h, z23.h, #0xfff9 label
26 orr z0.s, z0.s, #0xfffffff9 label
38 orr z5.b, z5.b, #0x6 label
44 orr z23.h, z23.h, #0x6 label
50 orr z0.s, z0.s, #0x6 label
56 orr z0.d, z0.d, #0x6 label
120 orr z0.s, z0.s, z0.s label
126 orr z0.h, z0.h, z0.h label
132 orr z0.b, z0.b, z0.b label
[all …]
H A Dorr-diagnostics.s6 orr z5.b, z5.b, #0xfa label
11 orr z5.b, z5.b, #0xfff9 label
16 orr z5.h, z5.h, #0xfffa label
21 orr z5.h, z5.h, #0xfffffff9 label
26 orr z5.s, z5.s, #0xfffffffa label
44 orr z7.d, z8.d, #254 label
49 orr z0.d, p0/m, z1.d, z2.d label
55 orr z21.d, z5.d, z26.b label
64 orr z0.d, p8/z, z0.d, z1.d label
73 orr p0.h, p0/z, p0.h, p1.h label
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dreduce-or.ll34 ; GISEL-NEXT: orr w8, w8, w9
59 ; GISEL-NEXT: orr w8, w8, w9
60 ; GISEL-NEXT: orr w9, w10, w11
61 ; GISEL-NEXT: orr w8, w8, w9
92 ; GISEL-NEXT: orr w8, w8, w9
97 ; GISEL-NEXT: orr w8, w8, w10
98 ; GISEL-NEXT: orr w9, w9, w11
100 ; GISEL-NEXT: orr w8, w8, w9
132 ; GISEL-NEXT: orr w8, w8, w9
150 ; GISEL-NEXT: orr w8, w8, w9
[all …]
H A Darm64-isel-or.ll11 ; CHECK-NEXT: orr w8, w0, w0, lsr #15
12 ; CHECK-NEXT: orr w8, w8, w8, lsr #15
13 ; CHECK-NEXT: orr w8, w8, w8, lsr #15
14 ; CHECK-NEXT: orr w0, w8, w8, lsr #15
31 ; CHECK-NEXT: orr w8, w0, w0, lsl #15
32 ; CHECK-NEXT: orr w8, w8, w8, lsl #15
33 ; CHECK-NEXT: orr w8, w8, w8, lsl #15
34 ; CHECK-NEXT: orr w0, w8, w8, lsl #15
H A Dicmp-shift-opt.ll15 ; CHECK-NEXT: orr x8, x1, x0, lsr #60
34 ; CHECK-NEXT: orr x8, x1, x0, lsr #17
46 ; CHECK-NEXT: orr x8, x1, x0, lsr #17
58 ; CHECK-NEXT: orr x8, x0, x1, lsl #17
70 ; CHECK-NEXT: orr x8, x0, x1, lsl #17
86 ; CHECK-NEXT: orr x8, x0, x1
104 ; CHECK-NEXT: orr x8, x1, x0, lsl #17
123 ; CHECK-NEXT: orr x8, x8, x1, lsl #18
139 ; CHECK-NEXT: orr x8, x2, x0
143 ; CHECK-NEXT: orr x9, x10, x9
[all …]
H A Dunfold-masked-merge-scalar-variablemask.ll11 ; CHECK-NEXT: orr w0, w9, w8
25 ; CHECK-NEXT: orr w0, w9, w8
39 ; CHECK-NEXT: orr w0, w9, w8
53 ; CHECK-NEXT: orr x0, x9, x8
70 ; CHECK-NEXT: orr w0, w9, w8
83 ; CHECK-NEXT: orr w0, w9, w8
96 ; CHECK-NEXT: orr w0, w9, w8
109 ; CHECK-NEXT: orr x0, x9, x8
124 ; CHECK-NEXT: orr w0, w9, w8
136 ; CHECK-NEXT: orr w0, w9, w8
[all …]
H A Dsetcc-fsh.ll12 ; CHECK-NEXT: orr w8, w0, w1, lsl #5
25 ; CHECK-NEXT: orr w8, w0, w1, lsl #5
39 ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
66 ; CHECK-NEXT: orr w8, w0, w1, lsl #8
79 ; CHECK-NEXT: orr w8, w0, w1, lsl #8
92 ; CHECK-NEXT: orr x8, x0, x1, lsr #3
105 ; CHECK-NEXT: orr w8, w0, w1, lsl #7
118 ; CHECK-NEXT: orr w8, w0, w1, lsl #7
186 ; CHECK-NEXT: orr w8, w0, w8, lsr #2
200 ; CHECK-NEXT: orr w8, w0, w8, lsr #2
[all …]
H A Dcmp-select-sign.ll8 ; CHECK-NEXT: orr w0, w8, #0x1
19 ; CHECK-NEXT: orr w0, w8, #0x1
30 ; CHECK-NEXT: orr w0, w8, #0x1
41 ; CHECK-NEXT: orr w0, w8, #0x1
52 ; CHECK-NEXT: orr w0, w8, #0x1
63 ; CHECK-NEXT: orr x0, x8, #0x1
154 ; CHECK-NEXT: orr v0.4s, #1
165 ; CHECK-NEXT: orr v0.4s, #1
181 ; CHECK-NEXT: orr v2.4s, #1
248 ; CHECK-NEXT: orr x9, x8, #0x1
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dneon-mov.s102 orr v0.2s, #1
103 orr v1.2s, #0
104 orr v0.2s, #1, lsl #8
105 orr v0.2s, #1, lsl #16
106 orr v0.2s, #1, lsl #24
107 orr v0.4s, #1
108 orr v0.4s, #1, lsl #8
109 orr v0.4s, #1, lsl #16
110 orr v0.4s, #1, lsl #24
111 orr v31.4h, #1
[all …]
H A Darm64-aliases.s27 orr x2, xzr, x9
29 orr w2, wzr, w9
191 orr w15, wzr, #0xaaaaaaaa
198 orr x3, xzr, #0x1
199 orr w3, wzr, #0x1
200 orr x3, xzr, #0x10000
201 orr w3, wzr, #0x10000
204 ; CHECK: orr x3, xzr, #0x1
205 ; CHECK: orr w3, wzr, #0x1
213 orr w2, wzr, #0xfffffffe
[all …]
H A Darm64-logical-encoding.s34 orr w1, w2, #0x4000
35 orr x1, x2, #0x8000
40 orr w8, wzr, #0x1
41 orr x8, xzr, #0x1
182 orr w1, w2, w3
183 orr x1, x2, x3
184 orr w1, w2, w3, lsl #6
185 orr x1, x2, x3, lsl #6
186 orr w1, w2, w3, lsr #6
187 orr x1, x2, x3, lsr #6
[all …]
/llvm-project-15.0.7/libc/AOR_v20.02/string/aarch64/
H A Dstrcpy.S115 orr tmp2, tmp2, #REP8_7f
120 orr tmp4, tmp4, #REP8_7f
123 orr tmp2, data1, #REP8_7f
127 orr tmp4, data2, #REP8_7f
209 orr tmp2, data1, #REP8_7f
262 orr data1, data1, tmp2
263 orr data2a, data2, tmp2
283 orr tmp4, tmp4, data1a
289 orr tmp2, tmp2, #REP8_7f
291 orr tmp4, tmp4, #REP8_7f
[all …]
H A Dstrlen-mte.S82 orr tmp2, data1, REP8_7f
84 orr tmp4, data2, REP8_7f
105 orr tmp2, data2, REP8_7f
123 orr tmp2, tmp1, tmp3
129 orr tmp2, tmp1, tmp3
135 orr tmp2, data1, REP8_7f
136 orr tmp4, data2, REP8_7f
152 orr tmp2, data1, REP8_7f
168 orr tmp2, data1, REP8_7f
170 orr tmp4, data2, REP8_7f
[all …]
H A Dstrlen.S92 orr tmp2, data1, REP8_7f
94 orr tmp4, data2, REP8_7f
121 orr tmp2, tmp1, tmp3
127 orr tmp2, tmp1, tmp3
133 orr tmp2, data1, REP8_7f
134 orr tmp4, data2, REP8_7f
150 orr tmp2, data1, REP8_7f
166 orr tmp2, data1, REP8_7f
168 orr tmp4, data2, REP8_7f
175 orr tmp2, data1, REP8_7f
[all …]
H A Dstrcmp.S55 orr tmp2, data1, #REP8_7f
58 orr syndrome, diff, has_nul
95 orr tmp2, tmp3, #REP8_7f
98 orr syndrome, diff, has_nul
131 orr data1, data1, tmp2
132 orr data2, data2, tmp2
160 orr tmp2, data1, #REP8_7f
163 orr syndrome, diff, has_nul
H A Dstrnlen.S75 orr tmp2, data1, #REP8_7f
77 orr tmp4, data2, #REP8_7f
81 orr tmp1, has_nul1, has_nul2
86 orr tmp1, has_nul1, has_nul2
108 orr tmp2, data2, #REP8_7f
149 orr data1, data1, tmp2
150 orr data2a, data2, tmp2
H A Dstrchr.S81 orr vend1.16b, vhas_nul1.16b, vhas_chr1.16b
82 orr vend2.16b, vhas_nul2.16b, vhas_chr2.16b
100 orr vend1.16b, vhas_nul1.16b, vhas_chr1.16b
101 orr vend2.16b, vhas_nul2.16b, vhas_chr2.16b
102 orr vend1.16b, vend1.16b, vend2.16b
113 orr vend1.16b, vhas_nul1.16b, vhas_chr1.16b
114 orr vend2.16b, vhas_nul2.16b, vhas_chr2.16b
H A Dstrncmp.S71 orr tmp2, data1, #REP8_7f
97 orr has_nul, has_nul, mask
100 orr syndrome, diff, has_nul
134 orr tmp2, tmp3, #REP8_7f
137 orr syndrome, diff, has_nul
177 orr data1, data1, tmp2
178 orr data2, data2, tmp2
234 orr tmp2, data1, #REP8_7f
252 orr tmp2, data1, #REP8_7f
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dillegal-bitfield-loadstore.ll9 ; LE-NEXT: orr r1, r1, #384
17 ; BE-NEXT: orr r1, r2, r1, lsl #8
18 ; BE-NEXT: orr r1, r1, #384
33 ; LE-NEXT: orr r1, r1, #384
43 ; BE-NEXT: orr r1, r1, #1
58 ; LE-NEXT: orr r3, r3, #57088
68 ; BE-NEXT: orr r3, r3, #16711680
87 ; LE-NEXT: orr r1, r1, #384
99 ; BE-NEXT: orr r1, r1, #384
114 ; LE-NEXT: orr r1, r1, #384
[all …]
H A Dicmp-shift-opt.ll15 ; CHECK-NEXT: orr r2, r1, r0, lsr #16
35 ; CHECK-NEXT: orr r0, r1, r0, lsr #17
47 ; CHECK-NEXT: orr r0, r1, r0, lsr #17
59 ; CHECK-NEXT: orr r0, r0, r1, lsl #17
71 ; CHECK-NEXT: orr r0, r0, r1, lsl #17
87 ; CHECK-NEXT: orr r5, r0, r4, lsr #15
91 ; CHECK-NEXT: orr r0, r5, r4, lsl #17
106 ; CHECK-NEXT: orr r0, r1, r0, lsl #17
125 ; CHECK-NEXT: orr r0, r0, r1, lsr #15
146 ; CHECK-NEXT: orr r0, r2, r0
[all …]
H A Dunfold-shifts.ll10 ; CHECK: orr r0, r0, #255
13 ; CHECK-T2: orr r0, r0, #255
25 ; CHECK: orr r0, r0, #4080
28 ; CHECK-T2: orr r0, r0, #4080
40 ; CHECK: orr r0, r0, #65280
43 ; CHECK-T2: orr r0, r0, #65280
55 ; CHECK: orr r0, r0, #1044480
58 ; CHECK-T2: orr r0, r0, #1044480
71 ; CHECK: orr r0, r1, r0, lsl #6
144 ; CHECK: orr r2, r0, #4080
[all …]
H A Dumulo-128-legalisation-lowering.ll85 ; ARMV6-NEXT: orr r1, r1, r8
86 ; ARMV6-NEXT: orr r1, r1, r9
91 ; ARMV6-NEXT: orr r0, r0, r10
92 ; ARMV6-NEXT: orr r0, r0, r6
93 ; ARMV6-NEXT: orr r0, r0, r2
95 ; ARMV6-NEXT: orr r1, r1, r2
97 ; ARMV6-NEXT: orr r1, r2, r1
98 ; ARMV6-NEXT: orr r0, r1, r0
101 ; ARMV6-NEXT: orr r0, r0, r1
175 ; ARMV7-NEXT: orr r0, r0, r1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-vpt-blocks.ll4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
H A Dthumb2-orr2.ll9 ; CHECK: orr r0, r0, #187
17 ; CHECK: orr r0, r0, #11141290
25 ; CHECK: orr r0, r0, #-872363008
33 ; CHECK: orr r0, r0, #1145324612
41 ; CHECK: orr r0, r0, #1114112
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Darm-arithmetic-aliases.s36 orr r2, r2, #6 label
37 orr r2, #6 label
38 orr r2, r2, r3 label
39 orr r2, r3 label
41 @ CHECK: orr r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe3]
42 @ CHECK: orr r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe3]
43 @ CHECK: orr r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe1]
44 @ CHECK: orr r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe1]

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