| /llvm-project-15.0.7/flang/test/Semantics/ |
| H A D | symbol15.f90 | 49 real, pointer :: opc1 component
99 real, pointer :: opc1 component
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 5362 bits<4> opc1;
5375 let Inst{23-20} = opc1;
5387 bits<4> opc1;
5400 let Inst{23-20} = opc1;
5592 bits<3> opc1;
5599 let Inst{23-21} = opc1;
5639 bits<3> opc1;
5646 let Inst{23-21} = opc1;
5688 bits<4> opc1;
5694 let Inst{7-4} = opc1;
[all …]
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| H A D | ARMInstrThumb2.td | 4534 bits<3> opc1;
4541 let Inst{23-21} = opc1;
4559 bits<4> opc1;
4565 let Inst{7-4} = opc1;
4579 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4589 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4597 def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4651 bits<4> opc1;
4664 let Inst{23-20} = opc1;
4677 bits<4> opc1;
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.td | 213 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
214 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
222 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
223 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
229 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
231 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
250 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
252 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
261 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
263 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 4472 class BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn,
4479 let Inst{23-22} = opc1;
4512 class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn,
4514 : BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> {
4524 multiclass MemTagStore<bits<2> opc1, string insn> {
4526 BaseMemTagStore<opc1, 0b10, insn, "\t$Rt, [$Rn, $offset]", "",
4529 BaseMemTagStore<opc1, 0b11, insn, "\t$Rt, [$Rn, $offset]!",
4534 BaseMemTagStore<opc1, 0b01, insn, "\t$Rt, [$Rn], $offset",
10912 let Inst{15} = opc1;
10924 multiclass SIMDIndexedTiedComplexHSD<bit opc1, bit opc2, Operand rottype,
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 6194 unsigned opc1 = fieldFromInstruction(Val, 4, 4); in DecoderForMRRC2AndMCRR2() local
6222 Inst.addOperand(MCOperand::createImm(opc1)); in DecoderForMRRC2AndMCRR2()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrAVX512.td | 3158 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
3160 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode,
3163 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode,
|