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/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_ds.s315 ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
318 ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
321 ds_write2_b32 v1, v2, v3 offset0:127
324 ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
327 ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
354 ds_write2st64_b32 v1, v2, v3 offset0:127
1182 ds_read2_b32 v[5:6], v1 offset0:127
1212 ds_read2st64_b32 v[5:6], v1 offset0:127
1680 ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
2367 ds_read2_b64 v[5:8], v1 offset0:127
[all …]
H A Dgfx8_asm_ds.s315 ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
318 ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
321 ds_write2_b32 v1, v2, v3 offset0:127
324 ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
327 ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
354 ds_write2st64_b32 v1, v2, v3 offset0:127
1125 ds_read2_b32 v[5:6], v1 offset0:127
1155 ds_read2st64_b32 v[5:6], v1 offset0:127
1632 ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
2319 ds_read2_b64 v[5:8], v1 offset0:127
[all …]
H A Dgfx9_asm_ds.s315 ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
318 ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
321 ds_write2_b32 v1, v2, v3 offset0:127
324 ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
327 ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
354 ds_write2st64_b32 v1, v2, v3 offset0:127
1143 ds_read2_b32 v[5:6], v1 offset0:127
1173 ds_read2st64_b32 v[5:6], v1 offset0:127
1650 ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
2505 ds_read2_b64 v[5:8], v1 offset0:127
[all …]
H A Dgfx10_asm_ds.s1391 ds_write2_b32 v0, v1, v2 offset0:0 offset1:123
1406 ds_write2_b32 v0, v1, v2 offset0:123 offset1:0
4646 ds_read2_b32 v[5:6], v1 offset0:0 offset1:255
4652 ds_read2_b32 v[5:6], v1 offset0:127
4655 ds_read2_b32 v[5:6], v1 offset0:127 offset1:0
4658 ds_read2_b32 v[5:6], v1 offset0:127 offset1:1
4682 ds_read2st64_b32 v[5:6], v1 offset0:127
5150 ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
5951 ds_read2_b64 v[5:8], v1 offset0:0 offset1:255
5957 ds_read2_b64 v[5:8], v1 offset0:127
[all …]
H A Dgfx11_ds.s21 ds_wrxchg2_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
24 ds_wrxchg2st64_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
30 ds_read2_b32 v[254:255], v1 offset0:127 offset1:255
33 ds_read2st64_b32 v[254:255], v1 offset0:127 offset1:255
51 ds_write2_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
54 ds_write2st64_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
60 ds_wrxchg2_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
63 ds_wrxchg2st64_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
69 ds_read2_b64 v[252:255], v1 offset0:127 offset1:255
72 ds_read2st64_b64 v[252:255], v1 offset0:127 offset1:255
H A Dds.s38 ds_write2_b32 v2, v4, v6 offset0:4
42 ds_write2_b32 v2, v4, v6 offset0:4 offset1:8
50 ds_read2_b32 v[8:9], v2 offset0:4
54 ds_read2_b32 v[8:9], v2 offset0:4 offset1:8
250 ds_wrxchg2_rtn_b32 v[0:1], v0, v0, v0 offset0:127 offset1:255
258 ds_wrxchg2st64_rtn_b32 v[0:1], v0, v255, v0 offset0:127 offset1:255
459 ds_wrxchg2_rtn_b64 v[0:3], v0, v[1:2], v[0:1] offset0:127 offset1:255
467 ds_wrxchg2st64_rtn_b64 v[0:3], v255, v[0:1], v[0:1] offset0:127 offset1:255
H A Dds-err.s14 ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
22 ds_write2_b32 v2, v4, v6 offset0:1000000000
26 ds_write2_b32 v2, v4, v6 offset0:0x100
H A Dgfx90a_ldst_acc.s7234 ds_write2_b32 v1, a2, a3 offset0:127
7238 ds_write2_b32 v1, a2, a3 offset0:127
7278 ds_write2st64_b32 v1, a2, a3 offset0:127
8302 ds_read2_b32 a[6:7], v1 offset0:127
8306 ds_read2_b32 a[6:7], v1 offset0:127
8342 ds_read2st64_b32 a[6:7], v1 offset0:127
8346 ds_read2st64_b32 a[6:7], v1 offset0:127
10118 ds_read2_b64 a[6:9], v1 offset0:127
10122 ds_read2_b64 a[6:9], v1 offset0:127
10158 ds_read2st64_b64 a[6:9], v1 offset0:127
[all …]
/llvm-project-15.0.7/lld/MachO/Arch/
H A DARM64.cpp370 uint32_t ins1 = read32le(buf + hint.offset0); in applyAdrpAdd()
392 writeNop(buf + hint.offset0 + hint.delta[0]); in applyAdrpAdd()
404 uint32_t ins1 = read32le(buf + hint.offset0); in applyAdrpAdrp()
419 writeNop(buf + hint.offset0 + hint.delta[0]); in applyAdrpAdrp()
432 uint32_t ins1 = read32le(buf + hint.offset0); in applyAdrpLdr()
453 writeNop(buf + hint.offset0); in applyAdrpLdr()
476 uint32_t ins1 = read32le(buf + hint.offset0); in applyAdrpLdrGotLdr()
511 writeNop(buf + hint.offset0); in applyAdrpLdrGotLdr()
512 writeNop(buf + hint.offset0 + hint.delta[0]); in applyAdrpLdrGotLdr()
524 writeNop(buf + hint.offset0 + hint.delta[0]); in applyAdrpLdrGotLdr()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dds-combine-large-stride.ll17 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:72 offset1:172
18 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:144 offset1:244
19 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset0:88 offset1:188
59 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:144 offset1:164
60 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:184 offset1:204
61 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:224 offset1:244
62 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:8 offset1:28
106 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:88 offset1:188
107 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:144 offset1:244
108 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset0:72 offset1:172
[all …]
H A Dload-local-i16.ll99 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
424 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3
425 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
426 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7
456 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
458 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7
495 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:14 offset1:15
497 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3
498 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
499 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7
[all …]
H A Dfence-lds-read2-write2.ll19 ; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset0:132 offset1:198
20 ; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:8 offset1:74
21 ; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:140 offset1:206
29 ; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset0:132 offset1:198
30 ; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:8 offset1:74
31 ; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:140 offset1:206
H A Dds-combine-with-dependence.ll9 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
10 ; GCN-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:8
42 ; GCN: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:27
43 ; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
75 ; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
109 ; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
H A Dds_read2_offset_order.ll6 ; offset0 is larger than offset1
11 ; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:11 offset1:12
12 ; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:6 offset1:248
H A Ddagcombine-reassociate-bug.ll16 %offset0 = add i64 %offset, 1027
17 %ptr0 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset0
H A Dload-local-i32.ll69 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
82 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7{{$}}
83 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5{{$}}
84 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
86 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:6 offs…
87 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:4 offs…
88 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:2 offs…
H A Dds_read2_superreg.ll40 ; CI-DAG: ds_read2_b32 v[[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
115 ; CI-DAG: ds_read2_b64 [[VEC_HI:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
132 ; CI-DAG: ds_read2_b64 [[VEC4_7:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
133 ; CI-DAG: ds_read2_b64 [[VEC8_11:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:4 offset1:5{{$}}
134 ; CI-DAG: ds_read2_b64 [[VEC12_15:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:6 offset1:7{{$}}
175 ; CI-DAG: ds_read2_b32 v[[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]], v{{[0-9]+}} offset0:2 offset1:3{…
H A Dreduce-store-width-alignment.ll14 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
33 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
/llvm-project-15.0.7/llvm/test/tools/dsymutil/X86/
H A Dop-convert-offset.test3 # $ cat op-convert-offset0.c
18 # $ xcrun clang -g -O2 -c -target x86_64-apple-unknown-macho op-convert-offset0.c -emit-llvm
19 # $ llvm-link op-convert-offset1.bc op-convert-offset0.bc -o op-convert-offset.ll -S
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Deh-return32.ll18 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp)
36 ; CHECK: lw $4, [[offset0]]($sp)
60 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp)
76 ; CHECK: lw $4, [[offset0]]($sp)
H A Deh-return64.ll19 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp)
37 ; CHECK: ld $4, [[offset0]]($sp)
63 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp)
79 ; CHECK: ld $4, [[offset0]]($sp)
/llvm-project-15.0.7/polly/test/IstAstInfo/
H A Dsimple-run-time-condition.ll49 %offset0 = add nsw i64 %i, %p
50 %subscript0 = mul i64 %offset0, %m
73 %offset0.1 = add nsw i64 %i.1, %p
74 %subscript0.1 = mul i64 %offset0.1, %m
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dds_gfx11.txt3043 # GFX11: ds_load_2addr_b32 v[5:6], v1 offset0:127 ; encoding: [0x7f,0x00,0xdc,0xd8,0x01,0x00,0x…
3067 # GFX11: ds_load_2addr_b64 v[5:8], v1 offset0:127 ; encoding: [0x7f,0x00,0xdc,0xd9,0x01,0x00,0x…
3091 # GFX11: ds_load_2addr_stride64_b32 v[5:6], v1 offset0:127 ; encoding: [0x7f,0x00,0xe0,0xd8,0x01,0x…
3115 # GFX11: ds_load_2addr_stride64_b64 v[5:8], v1 offset0:127 ; encoding: [0x7f,0x00,0xe0,0xd9,0x01,0x…
3865 # GFX11: ds_store_2addr_b32 v0, v1, v2 offset0:123 ; encoding: [0x7b,0x00,0x38,0xd8,0x00,0x01,0x…
3868 # GFX11: ds_store_2addr_b32 v0, v1, v2 offset0:123 gds ; encoding: [0x7b,0x00,0x3a,0xd8,0x00,0x01,0…
3913 # GFX11: ds_store_2addr_b32 v0, v254, v253 offset0:123 ; encoding: [0x7b,0x00,0x38,0xd8,0x00,0xfe,0…
3916 # GFX11: ds_store_2addr_b32 v0, v254, v253 offset0:123 gds ; encoding: [0x7b,0x00,0x3a,0xd8,0x00,0x…
3961 # GFX11: ds_store_2addr_b32 v255, v1, v253 offset0:123 ; encoding: [0x7b,0x00,0x38,0xd8,0xff,0x01,0…
4009 # GFX11: ds_store_2addr_b32 v255, v254, v2 offset0:123 ; encoding: [0x7b,0x00,0x38,0xd8,0xff,0xfe,0…
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dpr25281.ll30 %offset0 = add i32 %tmp6, %channelIndex
31 %tmp7 = getelementptr float, float* %in_0, i32 %offset0
/llvm-project-15.0.7/llvm/test/Analysis/Delinearization/
H A Dmultidim_ivs_and_integer_offsets_3d.ll30 %offset0 = add nsw i64 %i, 3
31 %subscript0 = mul i64 %offset0, %m

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