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/llvm-project-15.0.7/llvm/utils/
H A Dschedcover.py13 models = set() variable
17 global table, models
21 models.add(model)
32 global table, models
36 models.discard("default")
37 models.discard("itinerary")
41 ordered_models.extend(sorted(models))
/llvm-project-15.0.7/clang/test/SemaTemplate/
H A Dinstantiate-var-template.cpp40 template<typename... T> A<T...> models; variable
41 …template<> struct B models<>; // expected-error {{incomplete type 'struct B'}} expected-note {{for… variable
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DCMakeLists.txt3 set(LLVM_INLINER_MODEL_PATH_DEFAULT "models/inliner-Oz")
12 "models/gen-inline-oz-test-model.py"
/llvm-project-15.0.7/llvm/docs/Proposals/
H A DVectorizationPlan.rst117 VPBasicBlock and VPRegionBlock, see below. VPBlockBase models the hierarchical
119 BasicBlock, a VPBlockBase models its control-flow successors and predecessors
132 VPRegionBlock is a subclass of VPBlockBase. It models a collection of
150 models a constant or a live-in Value in VPlan. It has users, which are of type
163 A VPInstruction is both a VPRecipe and a VPUser. It models a single
181 the Hierarchical CFG models the planned control-flow, and Recipes capture
202 This effectively models masks in VPlan, facilitating VPlan-based predication.
/llvm-project-15.0.7/libcxx/docs/DesignDocs/
H A DThreadingSupportAPI.rst11 Libc++ supports using multiple different threading models and configurations
13 These different models provide entirely different interfaces from each
/llvm-project-15.0.7/polly/test/ScopDetect/
H A Dnon-simple-memory-accesses.ll4 ; how to handle them correctly and the Alias Set Tracker models some of them
/llvm-project-15.0.7/llvm/cmake/modules/
H A DTensorFlowCompile.cmake33 message(WARNING "Autogenerated mock models should not be used in production builds.")
99 " Some reference models are also periodically released there.")
/llvm-project-15.0.7/llvm/test/CodeGen/MLRegalloc/
H A Ddev-rel-equivalence.ll15 ; RUN: %python %S/../../../lib/Analysis/models/gen-regalloc-eviction-test-model.py %t
H A Ddev-mode-logging.ll16 ; RUN: %python %S/../../../lib/Analysis/models/gen-regalloc-eviction-test-model.py %t
H A Ddev-mode-log-2-fcts.ll15 ; RUN: %python %S/../../../lib/Analysis/models/gen-regalloc-eviction-test-model.py %t
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCMakeLists.txt3 set(LLVM_RAEVICT_MODEL_PATH_DEFAULT "models/regalloc-eviction")
12 "../Analysis/models/gen-regalloc-eviction-test-model.py"
/llvm-project-15.0.7/llvm/test/Transforms/Inline/ML/
H A Dml-test-development-mode.ll10 ; RUN: %python %S/../../../../lib/Analysis/models/gen-inline-oz-test-model.py %t
H A Ddevelopment-training-log.ll5 ; RUN: %python %S/../../../../lib/Analysis/models/gen-inline-oz-test-model.py %t
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZ.td22 // SystemZ subtarget scheduling models
/llvm-project-15.0.7/llvm/docs/
H A DHowToUseInstrMappings.rst24 TableGen uses relationship models to map instructions with each other. These
25 models are described using ``InstrMapping`` class as a base. Each model sets
28 models and uses the information to construct relation tables which relate
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetInstrPredicate.td11 // MCInstPredicate definitions are used by target scheduling models to describe
33 // MCInstPredicate definitions are typically used by scheduling models to
285 // Instances of this class can be used by processor scheduling models to
302 // Used by processor models to describe dependency breaking instructions.
356 // Convenience classes and definitions used by processor scheduling models to
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dmisched-fp-basic.ll9 ; Check the latency of instructions for processors with sched-models
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Bufferization/TransformOps/
H A DBufferizationTransformOps.td39 external models must be registered when applying this transform op;
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmachine-combiner-madd.ll1 ; Test all AArch64 subarches with scheduling models.
H A Dglobal-merge-group-by-use.ll45 ; Sanity-check (don't worry about cost models) that we pick the biggest subset
/llvm-project-15.0.7/mlir/docs/Dialects/
H A DGPU.md28 require special buffers. Rationale: although the underlying models declare
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dppc64-calls.ll26 ; Calls to weak function requires a TOC restore 'nop' with all code models
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dpic-models.ll12 ; TODO: Check other relocation models?
/llvm-project-15.0.7/clang/test/Analysis/
H A Ddead-stores.m37 // This test case was a false positive due to how clang models
/llvm-project-15.0.7/mlir/include/mlir/Dialect/SPIRV/IR/
H A DSPIRVBarrierOps.td45 TessellationControl, GLCompute, or Kernel execution models. There is no

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