100cce417SJaved Absar; REQUIRES: asserts 2*1527baabSMatthias Braun; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a9 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ 300cce417SJaved Absar; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9 4*1527baabSMatthias Braun; RUN: llc < %s -mtriple=arm-eabi -mcpu=swift -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ 500cce417SJaved Absar; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT 6*1527baabSMatthias Braun; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ 700cce417SJaved Absar; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 800cce417SJaved Absar; 900cce417SJaved Absar; Check the latency of instructions for processors with sched-models 1000cce417SJaved Absar; 1100cce417SJaved Absar; Function Attrs: norecurse nounwind readnone 1200cce417SJaved Absardefine i32 @foo(float %a, float %b, float %c, i32 %d) local_unnamed_addr #0 { 1300cce417SJaved Absarentry: 1400cce417SJaved Absar; 1500cce417SJaved Absar; CHECK: ********** MI Scheduling ********** 1600cce417SJaved Absar; CHECK_A9: VADDS 1700cce417SJaved Absar; CHECK_SWIFT: VADDfd 1800cce417SJaved Absar; CHECK_R52: VADDS 1900cce417SJaved Absar; CHECK_A9: Latency : 5 2000cce417SJaved Absar; CHECK_SWIFT: Latency : 4 2100cce417SJaved Absar; CHECK_R52: Latency : 6 2200cce417SJaved Absar; 2300cce417SJaved Absar; CHECK_A9: VMULS 2400cce417SJaved Absar; CHECK_SWIFT: VMULfd 2500cce417SJaved Absar; CHECK_R52: VMULS 2600cce417SJaved Absar; CHECK_SWIFT: Latency : 4 2700cce417SJaved Absar; CHECK_A9: Latency : 6 2800cce417SJaved Absar; CHECK_R52: Latency : 6 2900cce417SJaved Absar; 3000cce417SJaved Absar; CHECK: VDIVS 3100cce417SJaved Absar; CHECK_SWIFT: Latency : 17 3200cce417SJaved Absar; CHECK_A9: Latency : 16 3300cce417SJaved Absar; CHECK_R52: Latency : 7 3400cce417SJaved Absar; 3500cce417SJaved Absar; CHECK: VCVTDS 3600cce417SJaved Absar; CHECK_SWIFT: Latency : 4 3700cce417SJaved Absar; CHECK_A9: Latency : 5 3800cce417SJaved Absar; CHECK_R52: Latency : 6 3900cce417SJaved Absar; 4000cce417SJaved Absar; CHECK: VADDD 4100cce417SJaved Absar; CHECK_SWIFT: Latency : 6 4200cce417SJaved Absar; CHECK_A9: Latency : 5 4300cce417SJaved Absar; CHECK_R52: Latency : 6 4400cce417SJaved Absar; 4500cce417SJaved Absar; CHECK: VMULD 4600cce417SJaved Absar; CHECK_SWIFT: Latency : 6 4700cce417SJaved Absar; CHECK_A9: Latency : 7 4800cce417SJaved Absar; CHECK_R52: Latency : 6 4900cce417SJaved Absar; 5000cce417SJaved Absar; CHECK: VDIVD 5100cce417SJaved Absar; CHECK_SWIFT: Latency : 32 5200cce417SJaved Absar; CHECK_A9: Latency : 26 5300cce417SJaved Absar; CHECK_R52: Latency : 17 5400cce417SJaved Absar; 5500cce417SJaved Absar; CHECK: VTOSIZD 5600cce417SJaved Absar; CHECK_SWIFT: Latency : 4 5700cce417SJaved Absar; CHECK_A9: Latency : 5 5800cce417SJaved Absar; CHECK_R52: Latency : 6 5900cce417SJaved Absar; 6000cce417SJaved Absar %add = fadd float %a, %b 6100cce417SJaved Absar %mul = fmul float %add, %add 6200cce417SJaved Absar %div = fdiv float %mul, %b 6300cce417SJaved Absar %conv1 = fpext float %div to double 6400cce417SJaved Absar %add3 = fadd double %conv1, %conv1 6500cce417SJaved Absar %mul4 = fmul double %add3, %add3 6600cce417SJaved Absar %div5 = fdiv double %mul4, %conv1 6700cce417SJaved Absar %conv6 = fptosi double %div5 to i32 6800cce417SJaved Absar ret i32 %conv6 6900cce417SJaved Absar} 70