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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmerge-m0.mir52 name: merge-m0-many-init
314 name: m0-in-loop-0
357 name: m0-in-loop-1
394 # GCN: $m0 = COPY %2
400 name: m0-in-loop-2
439 # GCN: $m0 = COPY %2
446 name: m0-in-loop-3
494 name: m0-in-loop-4
543 name: m0-in-loop-5
591 name: m0-in-loop-6
[all …]
H A Dset-gpr-idx-peephole.mir10 …_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
14 …_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
33 …S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mo…
55 …S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mo…
139 ; GCN: $m0 = S_MOV_B32 1
146 $m0 = S_MOV_B32 1
168 S_NOP 0, implicit-def $m0
184 S_SET_GPR_IDX_ON 1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode
187 S_SET_GPR_IDX_ON 1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode
204 S_SET_GPR_IDX_ON 1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode
[all …]
H A Dfold-operands-remove-m0-redef.mir41 $m0 = COPY %1
43 $m0 = COPY %1
67 $m0 = COPY %1
69 $m0 = COPY %1
70 $m0 = COPY %1
97 $m0 = COPY %1
99 $m0 = COPY %2
126 $m0 = COPY %1
128 $m0 = COPY %1
355 ; GCN-NEXT: $m0 = COPY $m0
[all …]
H A Ddebug-value-scheduler.mir35 %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0
41 %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0
42 %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0
43 %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0
44 %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0
45 %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0
46 %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0
47 %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0
48 %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0
49 %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0
[all …]
H A Dmachine-scheduler-sink-trivial-remats.mir62 %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0
63 %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0
64 %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0
65 %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0
66 %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0
67 %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0
68 %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0
69 %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0
70 %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0
71 %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0
[all …]
H A Dspill-m0.ll37 %m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0
46 %foo = call i32 asm sideeffect "s_add_i32 $0, $1, 1", "=s,{m0}"(i32 %m0) #0
86 ; GCN: ; def m0, 1
91 ; GCN: ; clobber m0
111 %m0 = call i32 asm sideeffect "; def $0, 1", "={m0}"() #0
131 ; FIXME-TOSMEM-NOT: m0
134 ; FIXME-TOSMEM-NOT: m0
165 ; TOSMEM-NOT: m0
167 ; TOSMEM: ; use m0
172 %m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0
[all …]
H A Dgws-hazards.mir19 ; GFX9-NEXT: $m0 = S_MOV_B32 -1
25 ; VI-NEXT: $m0 = S_MOV_B32 -1
31 ; CI-NEXT: $m0 = S_MOV_B32 -1
36 ; SI-NEXT: $m0 = S_MOV_B32 -1
43 $m0 = S_MOV_B32 -1
56 ; GFX9-NEXT: $m0 = S_MOV_B32 -1
61 ; VI-NEXT: $m0 = S_MOV_B32 -1
66 ; CI-NEXT: $m0 = S_MOV_B32 -1
70 ; SI-NEXT: $m0 = S_MOV_B32 -1
77 $m0 = S_MOV_B32 -1
[all …]
H A Dlocal-atomics64.ll7 ; GFX9-NOT: m0
19 ; GFX9-NOT: m0
32 ; GFX9-NOT: m0
45 ; GFX9-NOT: m0
58 ; GFX9-NOT: m0
70 ; GFX9-NOT: m0
89 ; GFX9-NOT: m0
104 ; GFX9-NOT: m0
117 ; GFX9-NOT: m0
129 ; GFX9-NOT: m0
[all …]
H A Ddebug-value-scheduler-liveins.mir18 %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0
24 %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0
25 %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0
26 %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0
27 %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0
28 %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0
29 %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0
30 %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0
31 %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0
32 %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0
[all …]
H A Dload-local-i1.ll8 ; GFX9-NOT: m0
25 ; GFX9-NOT: m0
34 ; GFX9-NOT: m0
43 ; GFX9-NOT: m0
52 ; GFX9-NOT: m0
61 ; GFX9-NOT: m0
70 ; GFX9-NOT: m0
79 ; GFX9-NOT: m0
88 ; GFX9-NOT: m0
101 ; GFX9-NOT: m0
[all …]
H A Dwaitcnt-vinterp.mir12 ; GFX11: $vgpr1 = LDS_PARAM_LOAD 0, 0, 0, implicit $m0, implicit $exec
13 ; GFX11: $vgpr2 = LDS_PARAM_LOAD 0, 1, 0, implicit $m0, implicit $exec
14 ; GFX11: $vgpr3 = LDS_PARAM_LOAD 0, 2, 0, implicit $m0, implicit $exec
15 ; GFX11: $vgpr4 = LDS_PARAM_LOAD 0, 3, 0, implicit $m0, implicit $exec
20 $vgpr1 = LDS_PARAM_LOAD 0, 0, 0, implicit $m0, implicit $exec
21 $vgpr2 = LDS_PARAM_LOAD 0, 1, 0, implicit $m0, implicit $exec
22 $vgpr3 = LDS_PARAM_LOAD 0, 2, 0, implicit $m0, implicit $exec
23 $vgpr4 = LDS_PARAM_LOAD 0, 3, 0, implicit $m0, implicit $exec
24 …$vgpr5 = V_INTERP_P10_F16_F32_inreg 0, $vgpr1, 0, $vgpr0, 0, $vgpr1, 0, 0, 2, implicit $m0, implic…
25 …$vgpr6 = V_INTERP_P10_F16_F32_inreg 0, $vgpr2, 0, $vgpr0, 0, $vgpr2, 0, 0, 2, implicit $m0, implic…
[all …]
H A Dlocal-atomics.ll11 ; GFX9-NOT: m0
27 ; GFX9-NOT: m0
41 ; GFX9-NOT: m0
58 ; GFX9-NOT: m0
74 ; GFX9-NOT: m0
88 ; GFX9-NOT: m0
107 ; GFX9-NOT: m0
122 ; GFX9-NOT: m0
136 ; GFX9-NOT: m0
155 ; GFX9-NOT: m0
[all …]
H A Dfold-reload-into-m0.mir4 # Test that a spill of a copy of m0 is not folded to be a spill of m0 directly.
18 ; CHECK-NEXT: S_NOP 0, implicit-def $m0
19 ; CHECK-NEXT: $sgpr0 = S_MOV_B32 $m0
24 ; CHECK-NEXT: $m0 = S_MOV_B32 killed $sgpr0
27 S_NOP 0, implicit-def $m0
28 %0:sreg_32 = COPY $m0
30 $m0 = COPY %0
31 S_SENDMSG 0, implicit $m0, implicit $exec
35 # Test that a reload into a copy of m0 is not folded to be a reload of m0 directly.
59 $m0 = COPY %0
[all …]
H A Dlds-dma-waitcnt.mir12 $m0 = S_MOV_B32 0
14 …$vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addr…
29 $m0 = S_MOV_B32 0
32 …$vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addr…
46 $m0 = S_MOV_B32 0
63 $m0 = S_MOV_B32 0
65 …$vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addr…
79 $m0 = S_MOV_B32 0
81 …$vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `i32 addr…
93 $m0 = S_MOV_B32 0
[all …]
H A Dhazard.mir7 # GCN: $m0 = S_MOV_B32
28 $m0 = S_MOV_B32 killed $sgpr7
37 # GCN: $m0 = S_MOV_B32
57 $m0 = S_MOV_B32 killed $sgpr7
75 $m0 = S_MOV_B32 killed $sgpr12
151 $m0 = S_MOV_B32 -1
167 $m0 = S_MOV_B32 -1
176 # GCN: $m0 = S_MOV_B32 0
183 $m0 = S_MOV_B32 0
188 # GCN: $m0 = S_MOV_B32 0
[all …]
H A Dlds-dma-hazards.mir4 # GCN: $m0 = S_MOV_B32 0
11 $m0 = S_MOV_B32 0
16 # GCN: $m0 = S_MOV_B32 0
23 $m0 = S_MOV_B32 0
24 BUFFER_STORE_LDS_DWORD $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec, implicit $m0
28 # GCN: $m0 = S_MOV_B32 0
35 $m0 = S_MOV_B32 0
36 GLOBAL_LOAD_LDS_DWORD $vgpr2_vgpr3, 0, 0, implicit $exec, implicit $m0
40 # GCN: $m0 = S_MOV_B32 0
47 $m0 = S_MOV_B32 0
[all …]
H A Dllvm.amdgcn.sendmsg.ll6 ; GCN: s_mov_b32 m0, 0
7 ; GCN-NOT: s_mov_b32 m0
16 ; GCN: s_mov_b32 m0, 0
17 ; GCN-NOT: s_mov_b32 m0
26 ; GCN: s_mov_b32 m0, 0
27 ; GCN-NOT: s_mov_b32 m0
36 ; GCN: s_mov_b32 m0, 0
37 ; GCN-NOT: s_mov_b32 m0
46 ; GCN: s_mov_b32 m0, 0
47 ; GCN-NOT: s_mov_b32 m0
[all …]
H A Dstore-local.ll9 ; GFX9-NOT: m0
24 ; GFX9-NOT: m0
38 ; GFX9-NOT: m0
52 ; GFX9-NOT: m0
67 ; GFX9-NOT: m0
82 ; GFX9-NOT: m0
108 ; GFX9-NOT: m0
128 ; GFX9-NOT: m0
147 ; GFX9-NOT: m0
170 ; GFX9-NOT: m0
[all …]
H A Dllvm.amdgcn.interp.f16.ll9 ; GFX9-32BANK-NEXT: s_mov_b32 m0, s2
23 ; GFX8-32BANK-NEXT: s_mov_b32 m0, s2
37 ; GFX8-16BANK-NEXT: s_mov_b32 m0, s2
63 ; GFX9-32BANK-NEXT: s_mov_b32 m0, 0
65 ; GFX9-32BANK-NEXT: s_mov_b32 s3, m0
67 ; GFX9-32BANK-NEXT: s_mov_b32 m0, s2
79 ; GFX8-32BANK-NEXT: s_mov_b32 m0, 0
95 ; GFX8-16BANK-NEXT: s_mov_b32 m0, 0
109 %mx = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0
127 ; GFX9-32BANK-NEXT: s_mov_b32 m0, 0
[all …]
H A Dload-local-i32.ll15 ; GFX9-NOT: m0
28 ; GFX9-NOT: m0
40 ; GFX9-NOT: m0
54 ; GFX9-NOT: m0
67 ; GFX9-NOT: m0
80 ; GFX9-NOT: m0
99 ; GFX9-NOT: m0
110 ; GFX9-NOT: m0
121 ; GFX9-NOT: m0
132 ; GFX9-NOT: m0
[all …]
H A Dsendmsg-m0-hazard.mir10 ; GCN: $m0 = S_MOV_B32 -1
13 ; GCN-NEXT: S_SENDMSG 3, implicit $exec, implicit $m0
16 $m0 = S_MOV_B32 -1
17 S_SENDMSG 3, implicit $exec, implicit $m0
25 ; GCN: $m0 = S_MOV_B32 -1
31 $m0 = S_MOV_B32 -1
32 S_SENDMSGHALT 3, implicit $exec, implicit $m0
40 ; GCN: $m0 = S_MOV_B32 -1
43 ; GCN-NEXT: S_TTRACEDATA implicit $m0
46 $m0 = S_MOV_B32 -1
[all …]
H A Datomic_load_local.ll6 ; GFX9-NOT: s_mov_b32 m0
7 ; CI-NEXT: s_mov_b32 m0
18 ; GFX9-NOT: s_mov_b32 m0
19 ; CI-NEXT: s_mov_b32 m0
31 ; GFX9-NOT: s_mov_b32 m0
32 ; CI-NEXT: s_mov_b32 m0
43 ; GFX9-NOT: s_mov_b32 m0
44 ; CI-NEXT: s_mov_b32 m0
57 ; CI-NEXT: s_mov_b32 m0
69 ; CI-NEXT: s_mov_b32 m0
[all …]
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dgfx8_asm_smem.s87 s_load_dword s5, s[2:3], m0
723 s_store_dword s1, s[4:5], m0
726 s_store_dword s101, s[4:5], m0
756 s_store_dword s1, s[6:7], m0
765 s_store_dword s1, vcc, m0
768 s_store_dword s1, tba, m0
771 s_store_dword s1, tma, m0
795 s_store_dwordx2 vcc, s[4:5], m0
798 s_store_dwordx2 tba, s[4:5], m0
801 s_store_dwordx2 tma, s[4:5], m0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinst-select-extract-vector-elt.mir23 ; MOVREL-NEXT: $m0 = COPY [[COPY1]]
31 ; GPRIDX-NEXT: $m0 = COPY [[COPY1]]
54 ; MOVREL-NEXT: $m0 = COPY [[COPY1]]
62 ; GPRIDX-NEXT: $m0 = COPY [[COPY1]]
85 ; MOVREL-NEXT: $m0 = COPY [[COPY1]]
93 ; GPRIDX-NEXT: $m0 = COPY [[COPY1]]
116 ; MOVREL-NEXT: $m0 = COPY [[COPY1]]
124 ; GPRIDX-NEXT: $m0 = COPY [[COPY1]]
147 ; MOVREL-NEXT: $m0 = COPY [[COPY1]]
155 ; GPRIDX-NEXT: $m0 = COPY [[COPY1]]
[all …]
H A Datomic_load_local.ll6 ; GFX9-NOT: s_mov_b32 m0
7 ; CI-NEXT: s_mov_b32 m0
18 ; GFX9-NOT: s_mov_b32 m0
19 ; CI-NEXT: s_mov_b32 m0
31 ; GFX9-NOT: s_mov_b32 m0
32 ; CI-NEXT: s_mov_b32 m0
43 ; GFX9-NOT: s_mov_b32 m0
44 ; CI-NEXT: s_mov_b32 m0
57 ; CI-NEXT: s_mov_b32 m0
69 ; CI-NEXT: s_mov_b32 m0
[all …]

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