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Searched refs:ldrexd (Results 1 – 25 of 32) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dgpr-paired-spill-thumbinst.ll9 %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
10 %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
11 %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
12 %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
13 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
14 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
15 %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
H A Datomic-64bit.ll23 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
54 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
85 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
116 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
147 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
174 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
203 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
223 ; Compiles down to a single ldrexd, except on M class devices where ldrexd
234 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
260 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
[all …]
H A Dgpr-paired-spill.ll6 %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
7 %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
8 %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
9 %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
10 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
11 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
12 %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
H A DPR15053.ll5 declare { i32, i32 } @llvm.arm.ldrexd(i8*) nounwind readonly
9 %0 = tail call { i32, i32 } @llvm.arm.ldrexd(i8* undef) nounwind
H A Dldstrex.ll9 ; CHECK: ldrexd
12 %ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p)
13 %0 = extractvalue %0 %ldrexd, 1
14 %1 = extractvalue %0 %ldrexd, 0
33 declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly
H A Dinlineasm-64bit.ll6 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
8 …%1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A te…
49 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
52 …%1 = tail call { i64, i64 } asm sideeffect "@ atomic64_set\0A1: ldrexd $0, ${0:H}, [$3]\0Aldrexd $…
H A Dldstrex-m.ll6 ; CHECK-NOT: ldrexd
22 ; CHECK-NOT: ldrexd
H A Datomic-load-store.ll250 ; ARM-NEXT: ldrexd r0, r1, [r0]
257 ; ARMOPTNONE-NEXT: ldrexd r2, r3, [r0]
266 ; THUMBTWO-NEXT: ldrexd r0, r1, [r0]
293 ; ARMV6-NEXT: ldrexd r0, r1, [r0]
317 ; ARM-NEXT: ldrexd r4, r5, [r0]
355 ; ARMOPTNONE-NEXT: ldrexd r4, r5, [r3]
387 ; THUMBTWO-NEXT: ldrexd r3, r9, [r0]
421 ; ARMV6-NEXT: ldrexd r4, r5, [r0]
H A Darm-modifier.ll64 ;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
65 …%0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* elementty…
H A Dcmpxchg-O0.ll85 ; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [[[ADDR]]]
104 ; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [[[ADDR]]]
123 ; CHECK: ldrexd
H A Datomic-ops-v8.ll89 ; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
377 ; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
473 ; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
780 ; CHECK: ldrexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
1143 ; CHECK: ldrexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
H A Datomicrmw_exclusive_monitor_ints.ll6795 ; CHECK-ARM8-NEXT: ldrexd r4, r5, [r3]
6851 ; CHECK-ARM6-NEXT: ldrexd r4, r5, [r3]
7005 ; CHECK-ARM8-NEXT: ldrexd r4, r5, [r3]
7061 ; CHECK-ARM6-NEXT: ldrexd r4, r5, [r3]
7215 ; CHECK-ARM8-NEXT: ldrexd r4, r5, [r3]
7271 ; CHECK-ARM6-NEXT: ldrexd r4, r5, [r3]
7425 ; CHECK-ARM8-NEXT: ldrexd r4, r5, [r3]
7481 ; CHECK-ARM6-NEXT: ldrexd r4, r5, [r3]
7637 ; CHECK-ARM8-NEXT: ldrexd r4, r5, [r3]
7695 ; CHECK-ARM6-NEXT: ldrexd r4, r5, [r3]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Darm-LDREXD-reencoding.txt9 # CHECK: ldrexd r0, r1, [r0] @ encoding: [0x9f,0x0f,0xb0,0xe1]
10 # CHECK: ldrexd r12, sp, [r1] @ encoding: [0x9f,0xcf,0xb1,0xe1]
11 # CHECK: ldrexd r12, sp, [r3] @ encoding: [0x9f,0xcf,0xb3,0xe1]
12 # CHECK: ldrexd r8, r9, [sp] @ encoding: [0x9f,0x8f,0xbd,0xe1]
13 # CHECK: ldrexd r12, sp, [lr] @ encoding: [0x9f,0xcf,0xbe,0xe1]
H A Dinvalid-thumbv7-xfail.txt5 # Undefined encodings for ldrexd/strexd
8 # FIXME: "ldrexd r8, r8, [r2]"
H A Dthumb-tests.txt170 # CHECK: ldrexd r8, r9, [r2]
H A Dinvalid-armv7.txt150 # Undefined encodings for ldrexd
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumb2-ldrexd-strexd.s7 ldrexd r0, r1, [r2]
10 @ CHECK: ldrexd r0, r1, [r2] @ encoding: [0xd2,0xe8,0x7f,0x01]
H A Dthumbv8m.s74 ldrexd r0, r1, [r2] label
H A Ddiagnostics.s328 @ Out of order Rt/Rt2 operands for ldrexd/strexd
329 ldrexd r4, r3, [r8]
333 @ CHECK-ERRORS: ldrexd r4, r3, [r8]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-ldxr-stxr.ll10 %ldrexd = tail call %0 @llvm.aarch64.ldxp(i8* %p)
11 %0 = extractvalue %0 %ldrexd, 1
12 %1 = extractvalue %0 %ldrexd, 0
187 %ldrexd = tail call %0 @llvm.aarch64.ldaxp(i8* %p)
188 %0 = extractvalue %0 %ldrexd, 1
189 %1 = extractvalue %0 %ldrexd, 0
/llvm-project-15.0.7/compiler-rt/lib/builtins/arm/
H A Dsync-ops.h46 LOCAL_LABEL(tryatomic_##op) : ldrexd r0, r1, [r12]; \
/llvm-project-15.0.7/llvm/test/Transforms/AtomicExpand/ARM/
H A Datomic-expansion-v7.ll102 ; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
375 ; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
H A Datomic-expansion-v8.ll226 ; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td530 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/
H A Dcortex-a57-basic-instructions.s271 ldrexd r6, r7, [r8]
1141 # CHECK-NEXT: 0 0 0.00 * U ldrexd r6, r7, [r8]
2018 # CHECK-NEXT: - - - - - - - - ldrexd r6, r7, [r8]

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