| /llvm-project-15.0.7/llvm/test/tools/llvm-objdump/ELF/ARM/ |
| H A D | v8a-subarch.s | 5 lda: label
6 lda r0, [r1] label
8 @ CHECK-LABEL:lda
9 @ CHECK: e1910c9f lda r0, [r1]
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| H A D | v8r-subarch.s | 8 lda: label
9 lda r0, [r1] label
11 @ CHECK-LABEL:lda
12 @ CHECK: e1910c9f lda r0, [r1]
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| /llvm-project-15.0.7/clang/test/CodeGen/PowerPC/ |
| H A D | builtins-ppc-xlcompat-cmplx.c | 348 long double _Complex test_xl_cmplxl(long double lda, long double ldb) { in test_xl_cmplxl() argument
349 return __cmplxl(lda, ldb); in test_xl_cmplxl()
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| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | load-store-acquire-release-v8.s | 30 lda r5, [r6]
33 @ CHECK: lda r5, [r6] @ encoding: [0x9f,0x5c,0x96,0xe1]
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| H A D | load-store-acquire-release-v8-thumb.s | 30 lda r5, [r6]
33 @ CHECK: lda r5, [r6] @ encoding: [0xd6,0xe8,0xaf,0x5f]
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| H A D | thumbv8m.s | 100 lda r1, [r2] label
|
| /llvm-project-15.0.7/polly/test/ScheduleOptimizer/ |
| H A D | vec-addr-space.ll | 17 define void @LU_decomp_kij_opt(i32 %n, i32 %lda, float addrspace(4)* %A, float addrspace(4)* %scrat…
28 %mul = mul nsw i32 %k.035, %lda
42 %mul7 = mul nsw i32 %i.033, %lda
|
| /llvm-project-15.0.7/llvm/test/MC/Sparc/ |
| H A D | sparc-mem-instructions.s | 46 ! CHECK: lda [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x86,0x10,0x76]
47 lda [%i0 + %l6] 131, %o2
|
| H A D | sparcv9-instructions.s | 53 ! V9: lda [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x86,0x10,0x76]
57 ! V8-NEXT: lda [%l0] 0xf0, %f29
58 ! V9: lda [%l0] 240, %f29 ! encoding: [0xfb,0x84,0x1e,0x00]
59 lda [%l0] 0xf0, %f29
|
| /llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/ |
| H A D | lsr-invalid-ptr-extend.ll | 60 define protected amdgpu_kernel void @baseregtest(i32 %n, i32 %lda) local_unnamed_addr {
99 %mul1 = mul nsw i32 %i, %lda
|
| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | load-store-acquire-release-v8-thumb.txt | 24 # CHECK: lda r5, [r6] @ encoding: [0xd6,0xe8,0xaf,0x5f]
|
| H A D | load-store-acquire-release-v8.txt | 23 # CHECK: lda r5, [r6] @ encoding: [0x9f,0x5c,0x96,0xe1]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | ldstrex-m.ll | 32 ; CHECK-V8: lda
|
| H A D | atomic-ops-m33.ll | 96 ; CHECK: lda r0, [r0]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | prefer-dqform.ll | 13 …le(4) %.n, [0 x %_elem_type_of_a]* %.a, i32* noalias dereferenceable(4) %.lda, [0 x %_elem_type_o…
145 %_val_lda_ = load i32, i32* %.lda, align 4
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrAliases.td | 498 def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>;
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARM.td | 159 "Has v8 acquire/release (lda/ldaex "
|
| H A D | ARMInstrThumb2.td | 1628 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>,
|
| H A D | ARMInstrInfo.td | 2853 NoItinerary, "lda", "\t$Rt, $addr", []>;
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | ds_write2.ll | 871 define amdgpu_kernel void @write2_sgemm_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb, float …
|
| H A D | ds_read2.ll | 1075 define amdgpu_kernel void @sgemm_inner_loop_read2_sequence(float addrspace(1)* %C, i32 %lda, i32 %l…
|