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/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dasimd-ld4.s6 ld4 {v0.s, v1.s, v2.s, v3.s}[0], [sp] label
8 ld4 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp] label
10 ld4 {v0.d, v1.d, v2.d, v3.d}[0], [sp] label
12 ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp] label
14 ld4 {v0.s, v1.s, v2.s, v3.s}[0], [sp], #16 label
16 ld4 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #32 label
18 ld4 {v0.d, v1.d, v2.d, v3.d}[0], [sp], #32 label
22 ld4 {v0.s, v1.s, v2.s, v3.s}[0], [sp], x0 label
24 ld4 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], x0 label
26 ld4 {v0.d, v1.d, v2.d, v3.d}[0], [sp], x0 label
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-intrinsics-ldN-reg+reg-addr-mode.ll174 define <vscale x 64 x i8> @ld4.nxv64i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) {
175 ; CHECK-LABEL: ld4.nxv64i8:
185 define <vscale x 32 x i16> @ld4.nxv32i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) {
186 ; CHECK-LABEL: ld4.nxv32i16:
196 ; CHECK-LABEL: ld4.nxv32f16:
206 ; CHECK-LABEL: ld4.nxv32bf16:
217 ; CHECK-LABEL: ld4.nxv16i32:
227 ; CHECK-LABEL: ld4.nxv16f32:
237 define <vscale x 8 x i64> @ld4.nxv8i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) {
238 ; CHECK-LABEL: ld4.nxv8i64:
[all …]
H A Dsve-intrinsics-ldN-reg+imm-addr-mode.ll325 ; CHECK-LABEL: ld4.nxv64i8:
336 ; CHECK-LABEL: ld4.nxv64i8_lower_bound:
347 ; CHECK-LABEL: ld4.nxv64i8_upper_bound:
394 ; CHECK-LABEL: ld4.nxv64i8_outside_lower_bound:
433 ; CHECK-LABEL: ld4.nxv32i16:
444 ; CHECK-LABEL: ld4.nxv32f16:
455 ; CHECK-LABEL: ld4.nxv32bf16:
467 ; CHECK-LABEL: ld4.nxv16i32:
478 ; CHECK-LABEL: ld4.nxv16f32:
490 ; CHECK-LABEL: ld4.nxv8i64:
[all …]
H A Dsve-intrinsics-ldN-sret-reg+reg-addr-mode.ll174 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld4.nxv6…
175 ; CHECK-LABEL: ld4.nxv64i8:
185 define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @ld4.nxv3…
186 ; CHECK-LABEL: ld4.nxv32i16:
196 ; CHECK-LABEL: ld4.nxv32f16:
206 ; CHECK-LABEL: ld4.nxv32bf16:
217 ; CHECK-LABEL: ld4.nxv16i32:
227 ; CHECK-LABEL: ld4.nxv16f32:
237 define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @ld4.nxv8…
238 ; CHECK-LABEL: ld4.nxv8i64:
[all …]
H A Dsve-intrinsics-ldN-sret-reg+imm-addr-mode.ll345 ; CHECK-LABEL: ld4.nxv64i8:
357 ; CHECK-LABEL: ld4.nxv64i8_lower_bound:
369 ; CHECK-LABEL: ld4.nxv64i8_upper_bound:
417 ; CHECK-LABEL: ld4.nxv64i8_outside_lower_bound:
456 ; CHECK-LABEL: ld4.nxv32i16:
468 ; CHECK-LABEL: ld4.nxv32f16:
480 ; CHECK-LABEL: ld4.nxv32bf16:
493 ; CHECK-LABEL: ld4.nxv16i32:
505 ; CHECK-LABEL: ld4.nxv16f32:
518 ; CHECK-LABEL: ld4.nxv8i64:
[all …]
H A Daarch64-interleaved-ld-combine.ll25 ; AS: ld4
35 %ld4 = load <4 x float>, <4 x float>* %gep4, align 16
38 %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
39 %sv4 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
97 %ld4 = load <4 x float>, <4 x float>* %gep4, align 16
100 %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
101 %sv4 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
158 %ld4 = load <4 x float>, <4 x float>* %gep4, align 4
271 ; AS-NOT: ld4
308 ; AS-NOT: ld4
[all …]
H A Darm64-neon-vector-list-spill.ll49 ; CHECK: ld4 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}]
53 …%vld = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16…
109 ; CHECK: ld4 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [{{x[0-9]+|sp}…
113 …%vld = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(…
129 declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16(i16*)
132 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(i8*)
H A Dsve-intrinsics-loads.ll495 …%res = call <vscale x 64 x i8> @llvm.aarch64.sve.ld4.nxv64i8.nxv16i1.p0i8(<vscale x 16 x i1> %pred…
508 …%res = call <vscale x 32 x i16> @llvm.aarch64.sve.ld4.nxv32i16.nxv8i1.p0i16(<vscale x 8 x i1> %pre…
561 …%res = call <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0i64(<vscale x 2 x i1> %pred,…
611 declare <vscale x 64 x i8> @llvm.aarch64.sve.ld4.nxv64i8.nxv16i1.p0i8(<vscale x 16 x i1>, i8*)
612 declare <vscale x 32 x i16> @llvm.aarch64.sve.ld4.nxv32i16.nxv8i1.p0i16(<vscale x 8 x i1>, i16*)
613 declare <vscale x 16 x i32> @llvm.aarch64.sve.ld4.nxv16i32.nxv4i1.p0i32(<vscale x 4 x i1>, i32*)
614 declare <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0i64(<vscale x 2 x i1>, i64*)
615 declare <vscale x 32 x half> @llvm.aarch64.sve.ld4.nxv32f16.nxv8i1.p0f16(<vscale x 8 x i1>, half*)
616 declare <vscale x 32 x bfloat> @llvm.aarch64.sve.ld4.nxv32bf16.nxv8i1.p0bf16(<vscale x 8 x i1>, bfl…
617 declare <vscale x 16 x float> @llvm.aarch64.sve.ld4.nxv16f32.nxv4i1.p0f32(<vscale x 4 x i1>, float*)
[all …]
H A Darm64-indexed-vector-ldst.ll1514 …%ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(…
1526 …%ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(…
1541 …%ld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4.v8i8.p0i8(i8* %…
1553 …%ld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4.v8i8.p0i8(i8* %…
1568 …%ld4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4.v8i16.p0i16…
1581 …%ld4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4.v8i16.p0i16…
1596 …%ld4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16…
1609 …%ld4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16…
1624 …%ld4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32.p0i32…
1637 …%ld4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32.p0i32…
[all …]
H A Darm64-ld1.ll29 ; CHECK: ld4.8b { v0, v1, v2, v3 }, [x0]
64 ; CHECK: ld4.16b { v0, v1, v2, v3 }, [x0]
99 ; CHECK: ld4.4h { v0, v1, v2, v3 }, [x0]
134 ; CHECK: ld4.8h { v0, v1, v2, v3 }, [x0]
169 ; CHECK: ld4.2s { v0, v1, v2, v3 }, [x0]
204 ; CHECK: ld4.4s { v0, v1, v2, v3 }, [x0]
239 ; CHECK: ld4.2d { v0, v1, v2, v3 }, [x0]
344 ; CHECK: ld4.b { v0, v1, v2, v3 }[1], [x0]
375 ; CHECK: ld4.h { v0, v1, v2, v3 }[1], [x0]
406 ; CHECK: ld4.s { v0, v1, v2, v3 }[1], [x0]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/EarlyCSE/AArch64/
H A DldstN.ll6 declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0(ptr)
8 ; Although the store and the ld4 are using the same pointer, the
9 ; data can not be reused because ld4 accesses multiple elements.
13 …%0 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0(ptr undef)
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dneon-simd-ldst-multi-elem.s437 ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
438 ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
439 ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
441 ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
450 ld4 { v0.16b-v3.16b }, [x0]
451 ld4 { v15.8h-v18.8h }, [x15]
452 ld4 { v31.4s-v2.4s }, [sp]
453 ld4 { v0.2d-v3.2d }, [x0]
454 ld4 { v0.8b-v3.8b }, [x0]
455 ld4 { v15.4h-v18.4h }, [x15]
[all …]
H A Darm64-simd-ldst.s289 ld4.8b {v4, v5, v6, v7}, [x19]
290 ld4.16b {v4, v5, v6, v7}, [x19]
291 ld4.4h {v4, v5, v6, v7}, [x19]
292 ld4.8h {v4, v5, v6, v7}, [x19]
293 ld4.2s {v4, v5, v6, v7}, [x19]
294 ld4.4s {v4, v5, v6, v7}, [x19]
295 ld4.2d {v4, v5, v6, v7}, [x19]
1156 ld4.b {v4, v5, v6, v7}[13], [x3]
1157 ld4.h {v4, v5, v6, v7}[2], [x3]
1158 ld4.s {v4, v5, v6, v7}[2], [x3]
[all …]
H A Dneon-simd-ldst-one-elem.s114 ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
115 ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15]
116 ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp]
117 ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
275 ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
276 ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7
277 ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16
278 ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
H A Dneon-simd-post-ldst-multi-elem.s176 ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
177 ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
178 ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
179 ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
180 ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
181 ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
182 ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-ld4.mir26 …st4:fpr(<8 x s8>)= G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load…
55 …:fpr(<16 x s8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load…
84 …:fpr(<4 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load…
113 …4:fpr(<8 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load…
142 …4:fpr(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load…
171 …t4:fpr(<4 x s32>)= G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load…
200 …4:fpr(<2 x s64>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load…
229 …4:fpr(<2 x p0>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load…
258 …, %dst4:fpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load…
287 …), %dst4:fpr(p0) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load…
/llvm-project-15.0.7/clang/test/Sema/
H A Dwarn-literal-range.c35 long double ld4 = 0x0.42p-42000L; // expected-warning {{magnitude of floating-point constant too sm… variable
/llvm-project-15.0.7/clang/test/CodeGen/
H A Darm-vfp16-arguments.c31 float16x4_t ld4(void) { return g4; } in ld4() function
/llvm-project-15.0.7/llvm/test/Verifier/
H A Dintrinsic-arg-overloading-struct-ret.ll58 ; CHECK-NEXT: llvm.aarch64.neon.ld4.v4i32
60 …%res = call { <4 x i32>, <4 x i32>, <4 x i64>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32(<4 x i32>*…
63 declare { <4 x i32>, <4 x i32>, <4 x i64>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32(<4 x i32>* %ptr)
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dtsc-s116.ll50 %ld4 = load float, float* %gep4
54 %mul3 = fmul fast float %ld4, %ld3
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Darm64-advsimd.txt1295 # CHECK: ld4.8b { v1, v2, v3, v4 }, [x1]
1296 # CHECK: ld4.16b { v5, v6, v7, v8 }, [x2]
1297 # CHECK: ld4.2s { v10, v11, v12, v13 }, [x0]
1355 # CHECK: ld4.8b { v1, v2, v3, v4 }, [x2], x3
1356 # CHECK: ld4.16b { v2, v3, v4, v5 }, [x2], x4
1357 # CHECK: ld4.4h { v4, v5, v6, v7 }, [x3], x5
1358 # CHECK: ld4.8h { v7, v8, v9, v10 }, [x4], x6
1416 # CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3]
1417 # CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4]
1418 # CHECK: ld4.h { v3, v4, v5, v6 }[2], [x6]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Drevectorized_rdx_crash.ll61 %ld4 = load i32, i32* %i1, align 4
69 %i16 = add i32 %i15, %ld4
H A Dbswap.ll123 %ld4 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @src32, i32 0, i64 4), align 2
131 %bswap4 = call i32 @llvm.bswap.i32(i32 %ld4)
157 …%ld4 = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @src16, i16 0, i64 4), align…
165 %bswap4 = call i16 @llvm.bswap.i16(i16 %ld4)
200 …%ld4 = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @src16, i16 0, i64 4), ali…
216 %bswap4 = call i16 @llvm.bswap.i16(i16 %ld4)
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dspill-q.ll28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
71 %tmp2 = fadd <4 x float> %tmp1, %ld4
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dthumb2-spill-q.ll28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
71 %tmp2 = fadd <4 x float> %tmp1, %ld4

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