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/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dasimd-ld2.s6 ld2 {v0.s, v1.s}[0], [sp] label
8 ld2 {v0.2s, v1.2s}, [sp] label
10 ld2 {v0.d, v1.d}[0], [sp] label
12 ld2 {v0.2d, v1.2d}, [sp] label
14 ld2 {v0.s, v1.s}[0], [sp], #8 label
16 ld2 {v0.2s, v1.2s}, [sp], #16 label
20 ld2 {v0.2d, v1.2d}, [sp], #32 label
22 ld2 {v0.s, v1.s}[0], [sp], x0 label
24 ld2 {v0.2s, v1.2s}, [sp], x0 label
26 ld2 {v0.d, v1.d}[0], [sp], x0 label
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dselect-ext.ll15 %ld2 = load volatile i8, ptr %arrayidx1
16 %cond.v = select i1 %c, i8 %ld2, i8 %ld1
31 %ld2 = load volatile i16, ptr %q
32 %cond.v = select i1 %c, i16 %ld2, i16 %ext_ld1
51 %ld2 = load volatile i16, ptr %q
52 %cond.v = select i1 %c, i16 %ld2, i16 %ext_ld1
68 %ld2 = load volatile i8, ptr %arrayidx1
69 %cond.v = select i1 %c, i8 %ld2, i8 %ld1
88 %ld2 = load volatile <2 x i32>, ptr %arrayidx1
105 %ld2 = load volatile <2 x i32>, ptr %arrayidx1
[all …]
H A Datom-cmpb.ll17 %ld2 = load i8, ptr %incdec.ptr, align 1
19 %x5 = xor i8 %ld2, -1
20 %cmp34 = icmp ult i8 %ld2, %ld1
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dppcf128sf.ll4 @ld2 = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
15 %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
19 %3 = load ppc_fp128, ppc_fp128* @ld2, align 16
23 %5 = load ppc_fp128, ppc_fp128* @ld2, align 16
27 %7 = load ppc_fp128, ppc_fp128* @ld2, align 16
91 %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
104 %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
117 %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
130 %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
143 %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
[all …]
H A Dpr15632.ll6 @ld2 = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
11 %x = load ppc_fp128, ppc_fp128* @ld2, align 16
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-intrinsics-ldN-reg+reg-addr-mode.ll6 define <vscale x 32 x i8> @ld2.nxv32i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) {
7 ; CHECK-LABEL: ld2.nxv32i8:
17 define <vscale x 16 x i16> @ld2.nxv16i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) {
18 ; CHECK-LABEL: ld2.nxv16i16:
28 ; CHECK-LABEL: ld2.nxv16f16:
38 ; CHECK-LABEL: ld2.nxv16bf16:
48 define <vscale x 8 x i32> @ld2.nxv8i32(<vscale x 4 x i1> %Pg, i32 *%addr, i64 %a) {
49 ; CHECK-LABEL: ld2.nxv8i32:
59 ; CHECK-LABEL: ld2.nxv8f32:
70 ; CHECK-LABEL: ld2.nxv4i64:
[all …]
H A Daarch64-interleaved-ld-combine.ll33 %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
95 %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
156 %ld2 = load <4 x float>, <4 x float>* %gep2, align 4
188 ; AS: ld2
198 %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
234 %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
269 ; AS-NOT: ld2
282 %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
306 ; AS-NOT: ld2
315 %ld2 = load <4 x float>, <4 x float>* %gep2, align 16
[all …]
H A Dsve-intrinsics-ldN-reg+imm-addr-mode.ll13 ; CHECK-LABEL: ld2.nxv32i8:
24 ; CHECK-LABEL: ld2.nxv32i8_lower_bound:
35 ; CHECK-LABEL: ld2.nxv32i8_upper_bound:
46 ; CHECK-LABEL: ld2.nxv32i8_not_multiple_of_2:
83 ; CHECK-LABEL: ld2.nxv16i16:
94 ; CHECK-LABEL: ld2.nxv16f16:
105 ; CHECK-LABEL: ld2.nxv16bf16:
117 ; CHECK-LABEL: ld2.nxv8i32:
128 ; CHECK-LABEL: ld2.nxv8f32:
140 ; CHECK-LABEL: ld2.nxv4i64:
[all …]
H A Dsve-intrinsics-ldN-sret-reg+reg-addr-mode.ll6 define { <vscale x 16 x i8>, <vscale x 16 x i8> } @ld2.nxv32i8(<vscale x 16 x i1> %Pg, i8 *%addr, i…
7 ; CHECK-LABEL: ld2.nxv32i8:
17 define { <vscale x 8 x i16>, <vscale x 8 x i16> } @ld2.nxv16i16(<vscale x 8 x i1> %Pg, i16 *%addr, …
18 ; CHECK-LABEL: ld2.nxv16i16:
28 ; CHECK-LABEL: ld2.nxv16f16:
38 ; CHECK-LABEL: ld2.nxv16bf16:
48 define { <vscale x 4 x i32>, <vscale x 4 x i32> } @ld2.nxv8i32(<vscale x 4 x i1> %Pg, i32 *%addr, i…
49 ; CHECK-LABEL: ld2.nxv8i32:
59 ; CHECK-LABEL: ld2.nxv8f32:
70 ; CHECK-LABEL: ld2.nxv4i64:
[all …]
H A Dsve-intrinsics-ldN-sret-reg+imm-addr-mode.ll13 ; CHECK-LABEL: ld2.nxv32i8:
25 ; CHECK-LABEL: ld2.nxv32i8_lower_bound:
37 ; CHECK-LABEL: ld2.nxv32i8_upper_bound:
49 ; CHECK-LABEL: ld2.nxv32i8_not_multiple_of_2:
86 ; CHECK-LABEL: ld2.nxv16i16:
98 ; CHECK-LABEL: ld2.nxv16f16:
110 ; CHECK-LABEL: ld2.nxv16bf16:
123 ; CHECK-LABEL: ld2.nxv8i32:
135 ; CHECK-LABEL: ld2.nxv8f32:
148 ; CHECK-LABEL: ld2.nxv4i64:
[all …]
H A Darm64_32-neon.ll44 ; CHECK: ld2.d { v0, v1 }[0], [x0]
65 declare {%vec, %vec} @llvm.aarch64.neon.ld2.v2f64.p0i8(i8*)
69 ; CHECK: ld2.2d { v0, v1 }, [x0], [[OFFSET]]
71 %vecs = call {%vec, %vec} @llvm.aarch64.neon.ld2.v2f64.p0i8(i8* %addr)
83 ; CHECK: ld2.d { v0, v1 }[1], [x0], [[OFFSET]]
138 ; CHECK: ld2.2d { v0, v1 }, [x0], #32
140 %vecs = call {%vec, %vec} @llvm.aarch64.neon.ld2.v2f64.p0i8(i8* %addr)
H A Dsve-ld-post-inc.ll60 %ld2 = load i64, i64* %gep
61 %vec2 = insertelement <4 x i64> %A, i64 %ld2, i32 2
87 %ld2 = load double, double* %gep
88 %vec2 = insertelement <4 x double> %A, double %ld2, i32 2
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dneon-simd-ldst-multi-elem.s369 ld2 { v0.16b, v1.16b }, [x0]
371 ld2 { v31.4s, v0.4s }, [sp]
372 ld2 { v0.2d, v1.2d }, [x0]
373 ld2 { v0.8b, v1.8b }, [x0]
375 ld2 { v31.2s, v0.2s }, [sp]
384 ld2 { v0.16b-v1.16b }, [x0]
385 ld2 { v15.8h-v16.8h }, [x15]
386 ld2 { v31.4s-v0.4s }, [sp]
387 ld2 { v0.2d-v1.2d }, [x0]
388 ld2 { v0.8b-v1.8b }, [x0]
[all …]
H A Darm64-simd-ldst.s187 ld2.8b {v4, v5}, [x19]
188 ld2.16b {v4, v5}, [x19]
189 ld2.4h {v4, v5}, [x19]
190 ld2.8h {v4, v5}, [x19]
191 ld2.2s {v4, v5}, [x19]
192 ld2.4s {v4, v5}, [x19]
193 ld2.2d {v4, v5}, [x19]
1096 ld2.b {v4, v5}[13], [x3]
1097 ld2.h {v4, v5}[2], [x3]
1098 ld2.s {v4, v5}[2], [x3]
[all …]
H A Dneon-simd-ldst-one-elem.s96 ld2 { v0.b, v1.b }[9], [x0]
97 ld2 { v15.h, v16.h }[7], [x15]
98 ld2 { v31.s, v0.s }[3], [sp]
99 ld2 { v0.d, v1.d }[1], [x0]
257 ld2 { v0.b, v1.b }[9], [x0], x3
258 ld2 { v15.h, v16.h }[7], [x15], #4
259 ld2 { v31.s, v0.s }[3], [sp], #8
260 ld2 { v0.d, v1.d }[1], [x0], x0
H A Dneon-simd-post-ldst-multi-elem.s124 ld2 { v0.16b, v1.16b }, [x0], x1
125 ld2 { v15.8h, v16.8h }, [x15], x2
126 ld2 { v31.4s, v0.4s }, [sp], #32
127 ld2 { v0.2d, v1.2d }, [x0], #32
128 ld2 { v0.8b, v1.8b }, [x0], x2
129 ld2 { v15.4h, v16.4h }, [x15], x3
130 ld2 { v31.2s, v0.2s }, [sp], #16
/llvm-project-15.0.7/llvm/test/Bitcode/
H A Dintrinsics-struct-upgrade.ll5 declare %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2.v8i8.p0i8(i8*)
8 ; CHECK: %1 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0i8(i8* %A)
16 %val = call %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2.v8i8.p0i8(i8* %A)
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/SystemZ/
H A Dmem-interleaving-costs-02.ll16 ; CHECK: LV: Found an estimated cost of 0 for VF 4 For instruction: %ld2 = load i16
31 %ld2 = load i16, i16* %ptr2
35 %a2 = add i16 %a1, %ld2
80 ; CHECK: LV: Found an estimated cost of 0 for VF 2 For instruction: %ld2 = load i8
95 %ld2 = load i8, i8* %ptr2
99 %a2 = add i8 %a1, %ld2
120 ; CHECK: LV: Found an estimated cost of 0 for VF 2 For instruction: %ld2 = load i8
135 %ld2 = load i8, i8* %ptr2
139 %a2 = add i8 %a1, %ld2
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-ld2.mir22 …t2:fpr(<8 x s8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load…
45 …2:fpr(<16 x s8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load…
68 …2:fpr(<4 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load…
91 …2:fpr(<8 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load…
114 …2:fpr(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load…
137 …2:fpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load…
160 …2:fpr(<2 x s64>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load…
183 …t2:fpr(<2 x p0>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load…
206 …%dst1:fpr(s64), %dst2:fpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %pt…
229 …%dst1:fpr(p0), %dst2:fpr(p0) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(…
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dpromote-alloca-array-allocation.ll19 %ld2 = load i32, i32* %arrayidx10, align 4
20 store i32 %ld2, i32 addrspace(1)* %out, align 4
41 %ld2 = load i32, i32* %arrayidx10, align 4
42 store i32 %ld2, i32 addrspace(1)* %out, align 4
/llvm-project-15.0.7/llvm/test/Transforms/EarlyCSE/AArch64/
H A Dintrinsics.ll8 ; Check that @llvm.aarch64.neon.ld2 is optimized away by Early CSE.
10 ; CHECK-NOT: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0
27 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)
61 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)
74 ; Check that the first @llvm.aarch64.neon.ld2 is optimized away by Early CSE.
76 ; CHECK: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0
77 ; CHECK-NOT: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0
89 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)
106 ; Check that the store prevents @llvm.aarch64.neon.ld2 from being optimized
109 ; CHECK: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dbranch-targets.ll27 %ld2 = load i32, i32* %scevgep7, align 4
28 %mul = mul nsw i32 %ld2, %ld1
71 %ld2 = load i32, i32* %scevgep7, align 4
72 %mul = mul nsw i32 %ld2, %ld1
116 %mul = mul nsw i32 %ld2, %ld1
160 %mul = mul nsw i32 %ld2, %ld1
205 %mul = mul nsw i32 %ld2, %ld1
249 %mul = mul nsw i32 %ld2, %ld1
293 %mul = mul nsw i32 %ld2, %ld1
338 %mul = mul nsw i32 %ld2, %ld1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/AMDGPU/
H A Dunroll-analyze-small-loops.ll43 %ld2 = load float, float addrspace(5)* %arrayidx2, align 4
44 %mul3 = fmul contract float %M, %ld2
50 %mul4 = fmul contract float %ld2, %M
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dgeneric-to-nvvm.ll22 %ld2 = load i32, i32* @myconst
24 store i32 %ld2, i32* %b
/llvm-project-15.0.7/llvm/test/Transforms/SROA/
H A Dppcf128-no-fold.ll5 %struct.ld2 = type { [2 x ppc_fp128] }
11 %z = alloca %struct.ld2, align 16

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