Searched refs:isZeroExtended (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 119 static bool isZeroExtended(Register R, MachineRegisterInfo &MRI) { in isZeroExtended() function
157 (isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI))) in matchAArch64MulConstCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 701 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
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| H A D | PPCMIPeephole.cpp | 220 if (TII->isZeroExtended(*MI)) in getKnownLeadingZeroCount()
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| H A D | PPCInstrInfo.cpp | 2434 if (isZeroExtended(*MI)) { in optimizeCompareInstr()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 4244 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
4267 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
4361 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
4362 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
14302 isZeroExtended(N0.getNode(), DAG))) in performMulCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9319 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
9462 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
9482 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
9483 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
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