| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 416 bool isSub = Opc == sub; variable
417 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
447 bool isSub = Opc == sub; variable
448 return ((int)isSub << 8) | Offset | (IdxMode << 9);
490 bool isSub = Opc == sub; in getAM5Opc() local
491 return ((int)isSub << 8) | Offset; in getAM5Opc()
511 bool isSub = Opc == sub; in getAM5FP16Opc() local
512 return ((int)isSub << 8) | Offset; in getAM5FP16Opc()
|
| H A D | ARMInstPrinter.cpp | 378 bool isSub = OffImm < 0; in printThumbLdrLabelOperand() local
383 if (isSub) { in printThumbLdrLabelOperand()
1190 bool isSub = OffImm < 0; in printAddrModeImm12Operand() local
1194 if (isSub) { in printAddrModeImm12Operand()
1214 bool isSub = OffImm < 0; in printT2AddrModeImm8Operand() local
1218 if (isSub) { in printT2AddrModeImm8Operand()
1243 bool isSub = OffImm < 0; in printT2AddrModeImm8s4Operand() local
1250 if (isSub) { in printT2AddrModeImm8s4Operand()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 301 bool isSub = NumBytes < 0; in emitT2RegPlusImmediate() local
302 if (isSub) NumBytes = -NumBytes; in emitT2RegPlusImmediate()
326 if (isSub) { in emitT2RegPlusImmediate()
384 Opc = isSub ? t2SUB : t2ADD; in emitT2RegPlusImmediate()
537 bool isSub = false; in rewriteT2FrameIndex() local
569 isSub = true; in rewriteT2FrameIndex()
646 isSub = true; in rewriteT2FrameIndex()
664 isSub = true; in rewriteT2FrameIndex()
678 isSub = true; in rewriteT2FrameIndex()
732 if (isSub) { in rewriteT2FrameIndex()
[all …]
|
| H A D | ThumbRegisterInfo.cpp | 132 bool isSub = false; in emitThumbRegPlusImmInReg() local
138 isSub = true; in emitThumbRegPlusImmInReg()
169 int Opc = (isSub) ? ARM::tSUBrr in emitThumbRegPlusImmInReg()
174 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
192 bool isSub = NumBytes < 0; in emitThumbRegPlusImmediate() local
194 if (isSub) Bytes = -NumBytes; in emitThumbRegPlusImmediate()
227 ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate()
233 assert(!isSub && "Thumb1 does not have tSUBrSPi"); in emitThumbRegPlusImmediate()
242 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3; in emitThumbRegPlusImmediate()
250 ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8; in emitThumbRegPlusImmediate()
|
| H A D | ARMBaseInstrInfo.cpp | 2646 bool isSub = false; in rewriteARMFrameIndex() local
2663 isSub = true; in rewriteARMFrameIndex()
2750 isSub = true; in rewriteARMFrameIndex()
2765 if (isSub) { in rewriteARMFrameIndex()
2778 if (isSub) { in rewriteARMFrameIndex()
3467 if (!isSub && in getNumMicroOpsSwiftLdSt()
3483 if (!isSub && in getNumMicroOpsSwiftLdSt()
3511 if (!isSub && in getNumMicroOpsSwiftLdSt()
3524 if (!isSub && in getNumMicroOpsSwiftLdSt()
3575 if (!isSub && in getNumMicroOpsSwiftLdSt()
[all …]
|
| H A D | ARMISelLowering.cpp | 11886 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; in EmitInstrWithCustomInserter() local
11888 if (isSub) in EmitInstrWithCustomInserter()
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 222 bool isSub = NumBytes < 0; in emitSPUpdate() local
223 uint64_t Offset = isSub ? -NumBytes : NumBytes; in emitSPUpdate()
225 isSub ? MachineInstr::FrameSetup : MachineInstr::FrameDestroy; in emitSPUpdate()
248 if (isSub && !isEAXLiveIn(MBB)) in emitSPUpdate()
254 isSub ? getSUBrrOpcode(Is64Bit) : getADDrrOpcode(Is64Bit); in emitSPUpdate()
278 if (isSub) in emitSPUpdate()
305 unsigned Reg = isSub in emitSPUpdate()
309 unsigned Opc = isSub in emitSPUpdate()
313 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)) in emitSPUpdate()
320 BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue) in emitSPUpdate()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 2138 let Inst{30} = isSub;
2148 : BaseBaseAddSubCarry<isSub, regtype, asm,
2153 : BaseBaseAddSubCarry<isSub, regtype, asm,
2272 let Inst{15} = isSub;
2278 multiclass MulAccum<bit isSub, string asm> {
2293 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
2456 let Inst{30} = isSub;
2496 let Inst{30} = isSub;
2521 let Inst{30} = isSub;
2546 let Inst{30} = isSub;
[all …]
|
| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | CGExprScalar.cpp | 3602 bool isSub=false) { in tryEmitFMulAdd() argument
3618 return buildFMulAdd(LHSBinOp, op.RHS, CGF, Builder, false, isSub); in tryEmitFMulAdd()
3623 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub, false); in tryEmitFMulAdd()
3630 return buildFMulAdd(LHSBinOp, op.RHS, CGF, Builder, false, isSub); in tryEmitFMulAdd()
3636 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub, false); in tryEmitFMulAdd()
|