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Searched refs:isSpilledToReg (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DPrologEpilogInserter.cpp442 if (CS.isSpilledToReg()) in assignCalleeSavedSpillSlots()
545 if (I.isSpilledToReg()) { in updateLiveness()
571 if (CS.isSpilledToReg()) { in insertCSRSaves()
599 if (CI.isSpilledToReg()) { in insertCSRRestores()
H A DMIRPrinter.cpp447 if (!CSInfo.isSpilledToReg() && MFI.isDeadObjectIndex(FrameIdx)) in convertStackObjects()
452 if (!CSInfo.isSpilledToReg()) { in convertStackObjects()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp747 if (CSI.isSpilledToReg()) { in emitPrologue()
1196 if (I.isSpilledToReg()) { in emitPrologue()
1672 if (CSI.isSpilledToReg()) { in emitEpilogue()
2196 if (!GPRegs[i].isSpilledToReg()) { in processFunctionBeforeFrameFinalized()
2205 if (!G8Regs[i].isSpilledToReg()) { in processFunctionBeforeFrameFinalized()
2381 if (Info.isSpilledToReg()) { in spillCalleeSavedRegisters()
2440 if (I.isSpilledToReg()) { in spillCalleeSavedRegisters()
2612 if (CSI[i].isSpilledToReg()) { in restoreCalleeSavedRegisters()
H A DPPCRegisterInfo.cpp464 if (Info[i].isSpilledToReg()) in requiresFrameIndexScavenging()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineFrameInfo.h73 bool isSpilledToReg() const { return SpilledToReg; } in isSpilledToReg() function
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp528 assert(!Info.isSpilledToReg() && "Spilling to registers not implemented"); in emitCalleeSavedGPRLocations()
563 assert(!Info.isSpilledToReg() && "Spilling to registers not implemented"); in emitCalleeSavedSVELocations()