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Searched refs:isSignExtended (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp113 static bool isSignExtended(Register R, MachineRegisterInfo &MRI) { in isSignExtended() function
157 (isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI))) in matchAArch64MulConstCombine()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h695 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
H A DPPCMIPeephole.cpp856 TII->isSignExtended(*SrcMI)) { in simplifyCode()
H A DPPCInstrInfo.cpp2427 if (isSignExtended(*MI)) in optimizeCompareInstr()
H A DPPCISelLowering.cpp11490 static bool isSignExtended(MachineInstr &MI, const PPCInstrInfo *TII) { in isSignExtended() function
11495 return TII->isSignExtended(MI); in isSignExtended()
11559 isSignExtended(*RegInfo.getVRegDef(incr), TII); in EmitPartwordAtomicBinary()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4238 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended() function
4256 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
4356 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
4357 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
14301 if (N0->hasOneUse() && (isSignExtended(N0.getNode(), DAG) || in performMulCombine()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp9309 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended() function
9451 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
9477 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
9478 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()