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Searched refs:isSExt (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineFrameInfo.h179 bool isSExt = false; member
541 return Objects[ObjectIdx+NumFixedObjects].isSExt; in isObjectSExt()
547 Objects[ObjectIdx+NumFixedObjects].isSExt = IsSExt; in setObjectSExt()
H A DTargetCallingConv.h76 bool isSExt() const { return IsSExt; } in isSExt() function
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.cpp64 return LiveIn.second.isSExt(); in isLiveInSExt()
H A DPPCISelDAGToDAG.cpp5285 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
5288 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5294 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; in Select()
5300 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5305 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; in Select()
5322 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
5325 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5331 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; in Select()
5337 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
5342 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; in Select()
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H A DPPCISelLowering.cpp4259 if (Flags.isSExt()) in extendArgForPPC64()
5878 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in LowerCall_32SVR4()
6194 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4()
6655 LocInfo = ArgFlags.isSExt() ? CCValAssign::LocInfo::SExt in CC_AIX()
6845 if (Flags.isSExt()) in truncateScalarIntegerArg()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp859 bool isSExt = false; in select() local
863 isSExt = true; in select()
877 if (isSExt) { in select()
H A DARMFastISel.cpp2138 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in SelectRet()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td16 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
H A DAMDGPUCallLowering.cpp314 if (RetInfo.Flags[0].isSExt()) { in lowerReturnVal()
H A DSIISelLowering.cpp1695 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) && in convertArgType()
2479 DAG, VT, MemVT, DL, Chain, Offset, Alignment, Ins[i].Flags.isSExt(), &Ins[i]); in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp350 if (Flags.isSExt()) { in buildCopyFromRegs()
556 if (Flags.isSExt()) in extendOpFromFlags()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td12 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1598 Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall()
1611 StVal = DAG.getNode(Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND in LowerCall()
2622 unsigned Extend = Ins[InsIdx].Flags.isSExt() ? ISD::SIGN_EXTEND in LowerFormalArguments()
2700 Outs[i].Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerReturn()
2730 RetVal = DAG.getNode(Outs[i].Flags.isSExt() ? ISD::SIGN_EXTEND in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp1246 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1252 if (Outs[0].Flags.isSExt()) in X86SelectRet()
3241 if (Flags.isSExt()) in fastLowerCall()
H A DX86ISelLowering.cpp5032 Flags.isSExt() != MFI.isObjectSExt(FI)) { in MatchingStackOffset()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp378 if (ArgFlags.isSExt()) in CC_Lanai32_VarArg()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp506 if (ArgFlags.isSExt()) in AnalyzeArguments()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1750 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in selectRet()
H A DMipsISelLowering.cpp2886 if (ArgFlags.isSExt()) in CC_MipsO32()
2898 if (ArgFlags.isSExt()) in CC_MipsO32()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp877 bool isSExt; in getCopyFromRegs() local
881 isSExt = false; in getCopyFromRegs()
885 isSExt = true; in getCopyFromRegs()
891 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp323 Flags.isSExt() != MFI.isObjectSExt(FI)) { in MatchingStackOffset()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3838 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in selectRet()