Searched refs:isSEXTLoad (Results 1 – 4 of 4) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9310 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) in isSignExtended()
9403 assert((ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) && in SkipExtensionForVMULL()
19485 bool isSEXTLoad, SDValue &Base, in getARMIndexedAddressParts() argument
19544 bool isSEXTLoad, SDValue &Base, in getT2IndexedAddressParts() argument
19635 bool isSEXTLoad = false; in getPreIndexedAddressParts() local
19641 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPreIndexedAddressParts()
19650 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPreIndexedAddressParts()
19665 Ptr.getNode(), VT, Alignment, isSEXTLoad, IsMasked, in getPreIndexedAddressParts()
19693 bool isSEXTLoad = false, isNonExt; in getPostIndexedAddressParts() local
19699 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPostIndexedAddressParts()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 3044 inline bool isSEXTLoad(const SDNode *N) {
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6453 (ISD::isSEXTLoad(N0.getNode()) && N0.hasOneUse()))) { in visitAND()
11713 bool isAExtLoad = (ExtLoadType == ISD::SEXTLOAD) ? ISD::isSEXTLoad(N0Node) in tryToFoldExtOfExtload()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 9156 if (ISD::isSEXTLoad(InputNode)) in isValidSplatLoad()
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