| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | LiveRegUnits.h | 52 if (O->isRegMask()) in accumulateUsedDefed()
169 return MOP.isRegMask() || (MOP.isReg() && !MOP.isDebug() && in phys_regs_and_masks()
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| H A D | MachineOperand.h | 344 bool isRegMask() const { return OpKind == MO_RegisterMask; } in isRegMask() function
465 if ((isReg() && isImplicit()) || isRegMask()) in isValidExcessOperand()
640 assert(isRegMask() && "Wrong MachineOperand accessor"); in getRegMask()
708 assert(isRegMask() && "Wrong MachineOperand mutator"); in setRegMask()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | LiveRegUnits.cpp | 43 if (MOP.isRegMask()) { in stepBackward()
63 if (MOP.isRegMask()) { in accumulate()
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| H A D | LivePhysRegs.cpp | 47 if (MOP.isRegMask()) { in removeDefs()
99 } else if (O->isRegMask()) { in stepForward()
110 if (Reg.second->isRegMask() && in stepForward()
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| H A D | RegUsageInfoPropagate.cpp | 68 if (MO.isRegMask()) in setRegMask()
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| H A D | DeadMachineInstructionElim.cpp | 164 } else if (MO.isRegMask()) { in eliminateDeadMI()
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| H A D | CriticalAntiDepBreaker.cpp | 265 if (MO.isRegMask()) { in ScanInstruction()
373 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg)) in isNewRegClobberedByRefs()
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| H A D | MachineCopyPropagation.cpp | 249 if (MO.isRegMask()) in findAvailBackwardCopy()
281 if (MO.isRegMask()) in findAvailCopy()
753 if (MO.isRegMask()) in ForwardCopyPropagateBlock()
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| H A D | RegisterScavenging.cpp | 119 if (MO.isRegMask()) { in determineKillsAndDefs()
307 if (MO.isRegMask()) in findSurvivorReg()
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| H A D | MachineCSE.cpp | 240 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) in isPhysDefTriviallyDead()
382 if (MO.isRegMask()) in PhysRegDefsReach()
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| H A D | MachineInstrBundle.cpp | 322 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) { in AnalyzePhysRegInBundle()
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| H A D | ShrinkWrap.cpp | 301 } else if (MO.isRegMask()) { in INITIALIZE_PASS_DEPENDENCY()
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| H A D | RDFRegisters.cpp | 80 if (Op.isRegMask()) in PhysicalRegisterInfo()
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| H A D | ImplicitNullChecks.cpp | 242 auto IsRegMask = [](const MachineOperand &MO) { return MO.isRegMask(); }; in canHandle()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86VZeroUpper.cpp | 160 if (MI.isCall() && MO.isRegMask() && !clobbersAllYmmAndZmmRegs(MO)) in hasYmmOrZmmReg()
176 if (MO.isRegMask()) in callHasRegMask()
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| H A D | X86PreTileConfig.cpp | 110 MI.operands(), [](MachineOperand &MO) { return MO.isRegMask(); }); in isDestructiveCall()
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| /llvm-project-15.0.7/llvm/tools/llvm-reduce/deltas/ |
| H A D | ReduceRegisterMasks.cpp | 32 if (!MO.isRegMask()) in reduceMasksInFunction()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCTRLoopsVerify.cpp | 88 } else if (MO.isRegMask()) { in clobbersCTR()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AVR/ |
| H A D | rust-avr-bug-112.ll | 16 ; Assertion failed: ((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.cpp | 795 if (MO.isRegMask() && MO.clobbersPhysReg(DepReg)) in canPromoteToNewValueStore()
838 if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg)) in isImplicitDependency()
1283 if (!OpJ.isRegMask()) in hasRegMaskDependence()
1290 } else if (OpI.isRegMask()) { in hasRegMaskDependence()
1613 } else if (!Op.isRegMask()) { in isLegalToPacketizeTogether()
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| H A D | RDFDeadCode.cpp | 69 if (Op.isRegMask()) { in isLiveInstr()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 561 } else if (U.isRegMask()) { in colorChain()
697 } else if (MO.isRegMask()) { in maybeKillChain()
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| H A D | AArch64CollectLOH.cpp | 502 if (MO.isRegMask()) { in handleNormalInst()
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| /llvm-project-15.0.7/llvm/tools/llvm-reduce/ |
| H A D | ReducerWorkItem.cpp | 318 else if (DstMO.isRegMask()) { in cloneMF()
589 } else if (MO.isRegMask()) in computeMIRComplexityScoreImpl()
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| /llvm-project-15.0.7/llvm/unittests/CodeGen/ |
| H A D | MachineOperandTest.cpp | 54 ASSERT_TRUE(MO.isRegMask()); in TEST()
|