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Searched refs:isMoveReg (Results 1 – 25 of 31) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrDesc.h282 bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); } in isMoveReg() function
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenInstruction.h244 bool isMoveReg : 1; variable
H A DCodeGenInstruction.cpp376 isMoveReg = R->getValueAsBit("isMoveReg"); in CodeGenInstruction()
H A DInstrInfoEmitter.cpp1135 if (Inst.isMoveReg) OS << "|(1ULL<<MCID::MoveReg)"; in emitRecord()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrFPU.td166 let isMoveReg = 1;
173 let isMoveReg = 1;
590 let isMoveReg = 1 in {
594 } // isMoveReg
H A DMips16InstrInfo.cpp101 if (MI.isMoveReg()) in isCopyInstrImpl()
H A DMipsDSPInstrInfo.td455 bit isMoveReg = 1;
466 bit isMoveReg = 1;
510 bit isMoveReg = 1;
520 bit isMoveReg = 1;
H A DMicroMipsInstrInfo.td243 let isMoveReg = 1;
408 let isMoveReg = 1;
415 let isMoveReg = 1;
H A DMicroMipsInstrFPU.td132 let isMoveReg = 1;
H A DMips16InstrInfo.td870 let isMoveReg = 1;
881 let isMoveReg = 1;
892 let isMoveReg = 0;
H A DMipsSEInstrInfo.cpp238 } else if (MI.isMoveReg() || isORCopyInst(MI)) { in isCopyInstrImpl()
H A DMicroMipsDSPInstrInfo.td377 bit isMoveReg = 1;
H A DMipsMSAInstrInfo.td1808 bit isMoveReg = 1;
1903 bit isMoveReg = 1;
2457 bit isMoveReg = 1;
H A DMips64InstrInfo.td417 let isMoveReg = 1 in {
H A DMipsInstrInfo.td1732 let isMoveReg = 1;
1745 let isMoveReg = 1;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrMMX.td200 let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in {
207 } // SchedRW, hasSideEffects, isMoveReg
H A DX86InstrInfo.td1600 let hasSideEffects = 0, isMoveReg = 1 in {
1781 SchedRW = [WriteMove], isMoveReg = 1 in {
1848 let hasSideEffects = 0, isMoveReg = 1 in
/llvm-project-15.0.7/bolt/lib/Passes/
H A DTailDuplication.cpp178 (!BC.MII->get(OriginalInst.getOpcode()).isMoveReg() || in constantAndCopyPropagate()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineInstr.h908 bool isMoveReg(QueryType Type = IgnoreBundle) const {
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrVFP.td1121 let isMoveReg = 1 in {
1131 } // isMoveReg
1153 let isMoveReg = 1 in {
1200 } // isMoveReg
H A DARMInstrThumb.td1216 let hasSideEffects = 0, isMoveReg = 1 in {
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoC.td526 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
H A DRISCVInstrInfo.cpp1080 if (MI.isMoveReg()) in isCopyInstrImpl()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td537 bit isMoveReg = false; // Is this instruction a move register instruction?
/llvm-project-15.0.7/llvm/docs/TableGen/
H A DProgRef.rst1909 bit isMoveReg = 0;

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