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Searched refs:isKill (Results 1 – 25 of 141) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp164 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
165 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
197 bool DstIsKill = MI.getOperand(1).isKill(); in expandLogic()
198 bool SrcIsKill = MI.getOperand(2).isKill(); in expandLogic()
244 bool SrcIsKill = MI.getOperand(1).isKill(); in expandLogicImm()
298 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
352 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
417 bool DstIsKill = MI.getOperand(1).isKill(); in expand()
449 bool DstIsKill = MI.getOperand(1).isKill(); in expand()
487 bool DstIsKill = MI.getOperand(0).isKill(); in expand()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
225 bool AddRegKill = AddendMI->getOperand(1).isKill(); in processBlock()
226 bool KilledProdRegKill = MI.getOperand(KilledProdOp).isKill(); in processBlock()
227 bool OtherProdRegKill = MI.getOperand(OtherProdOp).isKill(); in processBlock()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp918 bool isKill = in rescheduleMIBelowKill() local
924 if (MOReg == Reg && !isKill) in rescheduleMIBelowKill()
1047 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS)); in rescheduleKillAboveMI() local
1048 if (MOReg == Reg && !isKill) in rescheduleKillAboveMI()
1051 if (isKill && MOReg != Reg) in rescheduleKillAboveMI()
1345 if (MO.isKill()) { in tryInstructionTransform()
1551 if (MO.isKill()) { in processTiedPairs()
1572 if (MO.isKill()) { in processTiedPairs()
1884 bool isKill = UseMO.isKill(); in eliminateRegSequence() local
1885 if (isKill) in eliminateRegSequence()
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H A DMachineInstrBundle.cpp167 if (MO.isKill()) in finalizeBundle()
176 if (MO.isKill()) in finalizeBundle()
226 bool isKill = KilledUseSet.count(Reg); in finalizeBundle() local
228 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
342 if (MO.isKill()) in AnalyzePhysRegInBundle()
H A DExpandPostRAPseudos.cpp76 if (MO.isKill() && TRI->regsOverlap(DstReg, MO.getReg())) in TransferImplicitOperands()
126 MI->getOperand(2).isKill()); in LowerSubregToReg()
172 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); in LowerCopy()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.h138 Register SrcReg, bool isKill, int FrameIndex, in storeRegToStackSlot() argument
141 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); in storeRegToStackSlot()
154 Register SrcReg, bool isKill, int FrameIndex,
H A DMipsSEFrameLowering.cpp193 .addReg(Src, getKillRegState(I->getOperand(0).isKill())); in expandStoreCCond()
235 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill()); in expandStoreACC()
267 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill()); in expandCopyACC()
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
390 TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0); in expandExtractElementF64()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp304 bool isKill = MI.getOperand(3).isKill(); in processSTVM() local
316 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3); in processSTVM()
384 bool isKill = MI.getOperand(3).isKill(); in processSTVM512() local
398 if (isKill) in processSTVM512()
410 if (isKill) { in processSTVM512()
H A DVEInstrInfo.cpp461 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
480 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
487 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
494 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
501 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
508 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
515 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
917 bool KillSrc = IsSrcReg ? MI.getOperand(2).isKill() : false; in expandPostRAPseudo()
964 bool KillSrc = MI.getOperand(1).isKill(); in expandPostRAPseudo()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp396 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
420 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
423 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
428 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
H A DSparcInstrInfo.h89 Register SrcReg, bool isKill, int FrameIndex,
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
H A DXCoreInstrInfo.h71 Register SrcReg, bool isKill, int FrameIndex,
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp38 Register SrcReg, bool isKill, int FrameIdx, in storeRegToStackSlot() argument
54 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
58 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
H A DMSP430InstrInfo.h44 Register SrcReg, bool isKill,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIPostRABundler.cpp178 if (Next != E && Next->isKill()) { in runOnMachineFunction()
186 while (Next != E && Next->isKill()) { in runOnMachineFunction()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineOperand.h389 bool isKill() const { in isKill() function
770 bool isKill = false, bool isDead = false,
801 bool isKill = false, bool isDead = false,
808 assert(!(isKill && isDef) && "Kill flag on def");
812 Op.IsDeadOrKill = isKill | isDead;
H A DMachineInstr.h1257 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1401 int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1406 MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
1408 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1413 Register Reg, bool isKill = false,
1416 findRegisterUseOperand(Reg, isKill, TRI);
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrBuilder.h158 unsigned Reg, bool isKill, int Offset) { in addRegOffset() argument
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp80 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
98 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
H A DThumb1InstrInfo.h45 Register SrcReg, bool isKill, int FrameIndex,
H A DThumb2InstrInfo.h46 Register SrcReg, bool isKill, int FrameIndex,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp237 if (Op.isReg() && Op.getReg() == RegNotKilled && Op.isKill()) in removeKillInfo()
757 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineIR()
804 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRI()
853 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineRR()
854 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRR()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.h40 bool isKill, int FrameIndex,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement()
436 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill()); in optimizeVectElement()
442 unsigned Src2IsKill = getKillRegState(MI.getOperand(3).isKill()); in optimizeVectElement()
642 StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill()); in processSeqRegInst()

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