| /llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParserCommon.h | 17 return isInt<8>(Value) || in isImmSExti16i8Value()
18 (isUInt<16>(Value) && isInt<8>(static_cast<int16_t>(Value))); in isImmSExti16i8Value()
22 return isInt<8>(Value) || in isImmSExti32i8Value()
23 (isUInt<32>(Value) && isInt<8>(static_cast<int32_t>(Value))); in isImmSExti32i8Value()
27 return isInt<8>(Value); in isImmSExti64i8Value()
31 return isInt<32>(Value); in isImmSExti64i32Value()
35 return isUInt<8>(Value) || isInt<8>(Value); in isImmUnsignedi8Value()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 31 Compressed = isInt<6>(Instr.Imm); in getInstSeqCost()
53 if (isInt<32>(Val)) { in generateInstSeqImpl()
112 if (!isInt<32>(Val)) { in generateInstSeqImpl()
118 if (ShiftAmount > 12 && !isInt<12>(Val)) { in generateInstSeqImpl()
119 if (isInt<32>((uint64_t)Val << 12)) { in generateInstSeqImpl()
276 if (isInt<32>(NewVal)) { in generateInstSeq()
319 if ((Val % 3) == 0 && isInt<32>(Val / 3)) { in generateInstSeq()
322 } else if ((Val % 5) == 0 && isInt<32>(Val / 5)) { in generateInstSeq()
325 } else if ((Val % 9) == 0 && isInt<32>(Val / 9)) { in generateInstSeq()
340 if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) { in generateInstSeq()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsAsmBackend.cpp | 81 if (!isInt<16>(Value)) { in adjustFixupValue()
91 if (!isInt<19>(Value)) { in adjustFixupValue()
130 if (!isInt<7>(Value)) { in adjustFixupValue()
140 if (!isInt<10>(Value)) { in adjustFixupValue()
150 if (!isInt<16>(Value)) { in adjustFixupValue()
159 if (!isInt<18>(Value)) { in adjustFixupValue()
172 if (!isInt<18>(Value)) { in adjustFixupValue()
181 if (!isInt<21>(Value)) { in adjustFixupValue()
190 if (!isInt<26>(Value)) { in adjustFixupValue()
199 if (!isInt<26>(Value)) { in adjustFixupValue()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.cpp | 318 return isInt<18>(BrOffset); in isBranchOffsetInRange()
334 return isInt<17>(BrOffset); in isBranchOffsetInRange()
338 return isInt<11>(BrOffset); in isBranchOffsetInRange()
342 return isInt<8>(BrOffset); in isBranchOffsetInRange()
347 return isInt<28>(BrOffset); in isBranchOffsetInRange()
371 return isInt<18>(BrOffset); in isBranchOffsetInRange()
375 return isInt<23>(BrOffset); in isBranchOffsetInRange()
379 return isInt<11>(BrOffset); in isBranchOffsetInRange()
383 return isInt<8>(BrOffset); in isBranchOffsetInRange()
387 return isInt<27>(BrOffset); in isBranchOffsetInRange()
[all …]
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| H A D | Mips16InstrInfo.cpp | 232 if (isInt<16>(-Remainder)) in makeFrame()
258 if (isInt<16>(Remainder)) in restoreFrame()
312 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16> in adjustStackPtr()
485 return isInt<16>(Amount); in validImmediate()
488 return isInt<16>(Amount); in validImmediate()
489 return isInt<15>(Amount); in validImmediate()
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| H A D | MipsSERegisterInfo.cpp | 216 if (OffsetBitSize < 16 && isInt<16>(Offset) && in eliminateFI()
236 } else if (!isInt<16>(Offset)) { in eliminateFI()
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelDAGToDAG.cpp | 96 return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0); in canBeRepresentedAsSls()
129 if (isInt<16>(CN->getSExtValue())) { in selectAddrRiSpls()
142 if (isInt<10>(CN->getSExtValue())) { in selectAddrRiSpls()
173 if ((RiMode && isInt<16>(CN->getSExtValue())) || in selectAddrRiSpls()
174 (!RiMode && isInt<10>(CN->getSExtValue()))) { in selectAddrRiSpls()
228 if (isInt<16>(CN->getSExtValue())) in selectAddrRr()
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| H A D | LanaiTargetTransformInfo.h | 67 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
69 if (isInt<21>(Imm.getZExtValue())) in getIntImmCost()
71 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
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| H A D | LanaiRegisterInfo.cpp | 165 if ((isSPLSOpcode(MI.getOpcode()) && !isInt<10>(Offset)) || in eliminateFrameIndex()
166 !isInt<16>(Offset)) { in eliminateFrameIndex()
181 if (!isInt<16>(Offset)) { in eliminateFrameIndex()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOperands.td | 13 def s8_0Imm64Pred : PatLeaf<(i64 imm), [{ return isInt<8>(N->getSExtValue()); }]>;
20 return isInt<32>(v);
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCFrameLowering.cpp | 67 else if (isInt<12>(AbsAmount)) in generateStackAdjustment()
140 else if (isInt<12>(VarArgsBytes)) in emitPrologue()
285 else if (isInt<12>(MoveAmount)) in emitEpilogue()
300 else if (isInt<12>(4 * StackSlotsUsedByFunclet)) in emitEpilogue()
327 else if (isInt<12>(VarArgsBytes)) in emitEpilogue()
457 else if (isInt<12>(NumBytes)) in emitRegUpdate()
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| H A D | ARCISelDAGToDAG.cpp | 111 if (!isInt<9>(RHSC)) in SelectAddrModeS9()
174 isInt<12>(CVal) ? ARC::MOV_rs12 : ARC::MOV_rlimm, in Select()
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| /llvm-project-15.0.7/clang-tools-extra/clang-tidy/altera/ |
| H A D | UnrollLoopsCheck.cpp | 183 if (!Evaluation || !Evaluation->isInt()) in hasLargeNumIterations()
244 if (!Result.Val.isInt()) in extractValue()
255 if (!Result.Val.isInt()) in exprHasLargeNumIterations()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVCodeGenPrepare.cpp | 136 if (!isUInt<32>(C) || isInt<12>(C) || !isInt<12>(SignExtend64<32>(C))) in optimizeAndExt()
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| H A D | RISCVMergeBaseOffset.cpp | 116 assert(isInt<32>(Offset) && "Unexpected offset"); in foldOffset()
180 if (!isInt<32>(Offset)) in matchLargeOffset()
234 assert(isInt<12>(Offset) && "Unexpected offset"); in matchShiftedOffset()
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| /llvm-project-15.0.7/mlir/lib/IR/ |
| H A D | BuiltinAttributes.cpp | 1142 static bool isValidIntOrFloat(Type type, int64_t dataEltSize, bool isInt, in isValidIntOrFloat() argument
1150 if (!isInt) in isValidIntOrFloat()
1176 bool isInt, in getRawIntOrFloat() argument
1179 isInt, isSigned); in getRawIntOrFloat()
1182 bool DenseElementsAttr::isValidIntOrFloat(int64_t dataEltSize, bool isInt, in isValidIntOrFloat() argument
1184 return ::isValidIntOrFloat(getElementType(), dataEltSize, isInt, isSigned); in isValidIntOrFloat()
1186 bool DenseElementsAttr::isValidComplex(int64_t dataEltSize, bool isInt, in isValidComplex() argument
1190 isInt, isSigned); in isValidComplex()
1403 bool isInt, in getRawComplex() argument
1407 dataEltSize / 2, isInt, isSigned)); in getRawComplex()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kAsmBackend.cpp | 173 if (!isInt<16>(Value)) { in fixupNeedsRelaxation()
183 return Value == 0 || !isInt<8>(Value); in fixupNeedsRelaxation()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAddSub.cpp | 232 if (isInt()) { in set()
243 if (!isInt()) in convertToFpType()
267 if (That.isInt()) in operator =()
275 if (isInt() == That.isInt()) { in operator +=()
276 if (isInt()) in operator +=()
283 if (isInt()) { in operator +=()
303 if (isInt() && That.isInt()) { in operator *=()
313 if (isInt()) in operator *=()
317 if (That.isInt()) in operator *=()
325 if (isInt()) in negate()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelDAGToDAG.cpp | 156 isInt<16>(IMMOffset->getZExtValue())) { in SelectADDRVTX_READ()
164 isInt<16>(IMMOffset->getZExtValue())) { in SelectADDRVTX_READ()
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| /llvm-project-15.0.7/mlir/lib/Dialect/Vector/Transforms/ |
| H A D | VectorTransforms.cpp | 155 if (isInt) { in createContractArithOp()
547 bool isInt = eltType.isa<IntegerType, IndexType>(); in matchAndRewrite() local
1319 if (isInt) in createAdd()
1328 if (isInt) in createMul()
1939 bool isInt = resType.isa<IntegerType>(); in lowerReduction() local
2710 type = isInt ? KindType::INT : KindType::FLOAT; in isValidKind()
2729 bool isInt = elType.isIntOrIndex(); in genOperator() local
2734 if (isInt) in genOperator()
2740 if (isInt) in genOperator()
2812 bool isInt = elType.isIntOrIndex(); in matchAndRewrite() local
[all …]
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| /llvm-project-15.0.7/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/ |
| H A D | RuntimeDyldCOFFAArch64.h | 318 assert(isInt<28>(PCRelVal) && "Branch target is out of range."); in resolveRelocation()
327 assert(isInt<21>(PCRelVal) && "Branch target is out of range."); in resolveRelocation()
336 assert(isInt<16>(PCRelVal) && "Branch target is out of range."); in resolveRelocation()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZOperands.td | 365 return isInt<8>(N->getSExtValue());
379 return isInt<16>(N->getSExtValue());
383 return isInt<16>(-N->getSExtValue());
400 return isInt<32>(-N->getSExtValue());
476 return isInt<8>(N->getSExtValue());
484 return isInt<16>(N->getSExtValue());
488 return isInt<16>(-N->getSExtValue());
496 return isInt<32>(N->getSExtValue());
500 return isInt<32>(-N->getSExtValue());
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| H A D | SystemZTargetTransformInfo.cpp | 87 if (isInt<32>(Imm.getSExtValue())) in getIntImmCost()
133 if (isInt<16>(Imm.getSExtValue())) in getIntImmCostInst()
140 if (isInt<32>(Imm.getSExtValue())) in getIntImmCostInst()
161 if (isInt<32>(Imm.getSExtValue())) in getIntImmCostInst()
256 if (isInt<32>(Imm.getSExtValue())) in getIntImmCostIntrin()
261 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) in getIntImmCostIntrin()
266 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) in getIntImmCostIntrin()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelDAGToDAG.cpp | 232 if (isInt<32>(CN->getSExtValue())) { in selectADDRzii()
263 if (isInt<32>(CN->getSExtValue())) { in selectADDRzi()
315 if (isInt<32>(CN->getSExtValue())) { in matchADDRri()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86OptimizeLEAs.cpp | 357 if (!isInt<32>(AddrDispShiftTemp)) in chooseBestLEA()
379 if (BestLEA != nullptr && !isInt<8>(AddrDispShiftTemp) && in chooseBestLEA()
380 isInt<8>(AddrDispShift)) in chooseBestLEA()
472 !isInt<32>(MI.getOperand(MemOpNo + X86::AddrDisp).getImm() + in isReplaceable()
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