| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 615 return isAdd; in EncodeAddrModeOpValues()
1021 if (isAdd) in getAddrModeImm12OpValue()
1052 if (isAdd) in getT2ScaledImmOpValue()
1100 if (isAdd) in getMveAddrModeQOpValue()
1144 if (isAdd) in getT2AddrModeImm8s4OpValue()
1171 if (isAdd) in getT2AddrModeImm7s4OpValue()
1277 if (isAdd) in getLdStSORegOpValue()
1424 bool isAdd; in getAddrMode5OpValue() local
1449 if (isAdd) in getAddrMode5OpValue()
1464 bool isAdd; in getAddrMode5FP16OpValue() local
[all …]
|
| H A D | ARMAsmBackend.cpp | 500 bool isAdd = true; in adjustFixupValue() local
503 isAdd = false; in adjustFixupValue()
509 Value |= isAdd << 23; in adjustFixupValue()
729 bool isAdd = true; in adjustFixupValue() local
732 isAdd = false; in adjustFixupValue()
749 bool isAdd = true; in adjustFixupValue() local
752 isAdd = false; in adjustFixupValue()
760 Value |= isAdd << 23; in adjustFixupValue()
776 bool isAdd = true; in adjustFixupValue() local
779 isAdd = false; in adjustFixupValue()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo16Instr.td | 59 let isCommutable = 1, isAdd = 1 in
64 let isCommutable = 1, isAdd = 1 in
69 let isAdd = 1 in
94 let isAdd = 1, Pattern = [(set mGPR:$rz, (add mGPR:$rZ, oimm8:$imm8))] in
100 let isAdd = 1 in
104 let isAdd = 1 in
114 let isAdd = 1 in
|
| H A D | CSKYInstrInfo.td | 469 let isAdd = 1 in
493 let isAdd = 1 in
548 let isCommutable = 1, isAdd = 1 in
|
| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 111 FLAG(isAdd) in EmitInstrDocs()
|
| H A D | CodeGenInstruction.h | 249 bool isAdd : 1; variable
|
| H A D | CodeGenInstruction.cpp | 381 isAdd = R->getValueAsBit("isAdd"); in CodeGenInstruction()
|
| H A D | InstrInfoEmitter.cpp | 1137 if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)"; in emitRecord()
|
| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 276 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd() function
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 871 bool isAdd; member
3283 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
3285 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
3294 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
3297 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
3304 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
3834 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
5645 bool isAdd = true; in parsePostIdxReg() local
5651 isAdd = false; in parsePostIdxReg()
5727 bool isAdd = true; in parseAM3Offset() local
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 3000 // {12} isAdd
3019 // {12} isAdd
3036 // {12} isAdd
3055 // {12} isAdd
3334 // {12} isAdd
3353 // {12} isAdd
3375 // {12} isAdd
3394 // {12} isAdd
3827 let isAdd = 1 in
3843 let isAdd = 1 in
[all …]
|
| H A D | ARMInstrFormats.td | 801 // {12} isAdd
819 // {12} isAdd
840 // {12} isAdd
893 // {8} isAdd
|
| H A D | ARMInstrThumb.td | 966 let isAdd = 1 in {
|
| H A D | ARMInstrThumb2.td | 2345 let isAdd = 1 in
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 442 if (DI->getDesc().isAdd()) { in findInductionRegister()
1624 if (DI->getDesc().isAdd()) { in fixupInductionVariable()
|
| H A D | HexagonDepInstrInfo.td | 220 let isAdd = 1;
236 let isAdd = 1;
|
| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | Target.td | 542 bit isAdd = false; // Is this instruction an add instruction?
|
| /llvm-project-15.0.7/llvm/docs/TableGen/ |
| H A D | ProgRef.rst | 1914 bit isAdd = 0;
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 46121 auto combineMulShlAddOrSub = [&](int Mult, int Shift, bool isAdd) { in combineMulSpecial() argument
46126 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
46131 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial() argument
46136 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
|