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Searched refs:is64BitVector (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DValueTypes.h180 bool is64BitVector() const { in is64BitVector() function
181 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1934 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2119 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
2149 if (!is64BitVector) in SelectVLD()
2264 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
2303 } else if (is64BitVector) { in SelectVST()
2420 bool is64BitVector = VT.is64BitVector(); in SelectVLDSTLane() local
2458 if (!is64BitVector) in SelectVLDSTLane()
2484 if (is64BitVector) in SelectVLDSTLane()
2493 if (is64BitVector) in SelectVLDSTLane()
2960 bool is64BitVector = VT.is64BitVector(); in SelectVLDDup() local
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H A DARMISelLowering.cpp6486 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP()
7337 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
7373 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
7411 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
7444 if (VT.is64BitVector() && EltSz == 32) in isVZIP_v_undef_Mask()
9518 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
9519 Op1.getValueType().is64BitVector() && in LowerMUL()
12411 if (!N->getValueType(0).is64BitVector()) in AddCombineToVPADD()
12450 if (!N00.getValueType().is64BitVector() || in AddCombineVUZPToVPADDL()
13995 if (VT.is64BitVector() || VT.is128BitVector()) in PerformMULCombine()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp139 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
H A DAArch64ISelLowering.cpp4397 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
4398 Op1.getValueType().is64BitVector() && in LowerMUL()
7875 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP_PARITY()
9458 if (SrcVT.is64BitVector()) in ReconstructShuffle()
9559 if (!SrcVT.is64BitVector()) { in ReconstructShuffle()
14669 if (!VT.is64BitVector() && !VT.is128BitVector()) in tryCombineToBSL()
14972 if (!VT.is64BitVector() && !VT.is128BitVector()) in performANDCombine()
15498 if (!VT.is64BitVector()) in tryExtendDUPToExtractHigh()
15503 if (N.getValueType().is64BitVector()) { in tryExtendDUPToExtractHigh()
16066 assert(LHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
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H A DAArch64FastISel.cpp2925 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2969 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
H A DAArch64ISelDAGToDAG.cpp172 if (!VT.is64BitVector() || !LVT.is128BitVector() || in SelectExtractHigh()
1443 } else if (VT == MVT::f64 || VT.is64BitVector()) { in tryIndexedLoad()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DMachineValueType.h406 bool is64BitVector() const { in is64BitVector() function
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp25704 assert(StoreVT.is64BitVector() && "Unexpected VT"); in LowerStore()
46975 N0.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()
46980 N1.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()