346                         bool is64BitVector);
1932                                        unsigned NumVecs, bool is64BitVector) {  in GetVLDSTAlign()  argument
1934   if (!is64BitVector && NumVecs < 3)  in GetVLDSTAlign()
2119   bool is64BitVector = VT.is64BitVector();  in SelectVLD()  local
2120   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVLD()
2149     if (!is64BitVector)  in SelectVLD()
2165   if (is64BitVector || NumVecs <= 2) {  in SelectVLD()
2166     unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVLD()
2234   unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);  in SelectVLD()
2264   bool is64BitVector = VT.is64BitVector();  in SelectVST()  local
2265   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVST()
2299   if (is64BitVector || NumVecs <= 2) {  in SelectVST()
2303     } else if (is64BitVector) {  in SelectVST()
2325     unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVST()
2420   bool is64BitVector = VT.is64BitVector();  in SelectVLDSTLane()  local
2458     if (!is64BitVector)  in SelectVLDSTLane()
2484     if (is64BitVector)  in SelectVLDSTLane()
2493     if (is64BitVector)  in SelectVLDSTLane()
2504   unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVLDSTLane()
2518   unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;  in SelectVLDSTLane()
2960   bool is64BitVector = VT.is64BitVector();  in SelectVLDDup()  local
2998   if (!is64BitVector)  in SelectVLDDup()
3014   unsigned Opc = is64BitVector    ? DOpcodes[OpcodeIndex]  in SelectVLDDup()
3030   if (is64BitVector || NumVecs == 1) {  in SelectVLDDup()
3063     unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;  in SelectVLDDup()