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/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dvplan-printing-outer-loop.ll16 ; CHECK-NEXT: WIDEN-PHI ir<%outer.iv> = phi ir<0>, ir<%outer.iv.next>
17 ; CHECK-NEXT: EMIT ir<%gep.1> = getelementptr ir<@arr2> ir<0> ir<%outer.iv>
18 ; CHECK-NEXT: EMIT store ir<%outer.iv> ir<%gep.1>
19 ; CHECK-NEXT: EMIT ir<%add> = add ir<%outer.iv> ir<%n>
24 ; CHECK-NEXT: WIDEN-PHI ir<%inner.iv> = phi ir<0>, ir<%inner.iv.next>
25 ; CHECK-NEXT: EMIT ir<%gep.2> = getelementptr ir<@arr> ir<0> ir<%inner.iv> ir<%outer.iv>
26 ; CHECK-NEXT: EMIT store ir<%add> ir<%gep.2>
27 ; CHECK-NEXT: EMIT ir<%inner.iv.next> = add ir<%inner.iv> ir<1>
28 ; CHECK-NEXT: EMIT ir<%inner.ec> = icmp ir<%inner.iv.next> ir<8>
35 ; CHECK-NEXT: EMIT ir<%outer.iv.next> = add ir<%outer.iv> ir<1>
[all …]
H A Dvplan-printing.ll70 ; CHECK-NEXT: WIDEN ir<%cmp> = icmp ir<%arrayidx>, ir<%z>
71 ; CHECK-NEXT: WIDEN-SELECT ir<%sel> = select ir<%cmp>, ir<1.000000e+01>, ir<2.000000e+01>
72 ; CHECK-NEXT: WIDEN ir<%add> = fadd ir<%lv>, ir<%sel>
208 ; CHECK-NEXT: WIDEN ir<%cmp> = icmp ir<%i>, ir<5>
292 ; CHECK-NEXT: WIDEN ir<%add> = add ir<%AB.0>, ir<%AB.1>
293 ; CHECK-NEXT: CLONE ir<%gep.CD.3> = getelementptr ir<@CD>, ir<0>, ir<%iv.plus.3>
404 ; CHECK-NEXT: WIDEN ir<%psd> = add ir<%lsd>, ir<23>
405 ; CHECK-NEXT: WIDEN ir<%cmp1> = icmp ir<%lsd>, ir<100>
409 ; CHECK-NEXT: WIDEN ir<%cmp2> = icmp ir<%lsd>, ir<200>
500 ; CHECK-NEXT: WIDEN ir<%v3> = add ir<%v2>, ir<1>
[all …]
H A Dvplan-sink-scalars-and-merge.ll40 ; CHECK-NEXT: REPLICATE ir<%add> = add ir<%lv.b>, ir<10>
41 ; CHECK-NEXT: REPLICATE ir<%mul> = mul ir<2>, ir<%add>
112 ; CHECK-NEXT: WIDEN ir<%mul> = mul ir<%iv>, ir<2>
122 ; CHECK-NEXT: REPLICATE ir<%gep.a> = getelementptr ir<@a>, ir<0>, ir<%mul>
192 ; CHECK-NEXT: WIDEN ir<%mul> = mul ir<%iv>, ir<%add>
201 ; CHECK-NEXT: REPLICATE ir<%gep.a> = getelementptr ir<@a>, ir<0>, ir<%mul>
257 ; CHECK-NEXT: WIDEN ir<%cmp> = icmp ir<%iv>, ir<%k>
330 ; CHECK-NEXT: WIDEN ir<%mul> = mul ir<%iv>, ir<10>
369 ; CHECK-NEXT: REPLICATE ir<%gep.a> = getelementptr ir<@a>, ir<0>, ir<%mul>
475 ; CHECK-NEXT: REPLICATE ir<%gep.a> = getelementptr ir<@a>, ir<0>, ir<%mul>
[all …]
H A Dfirst-order-recurrence-sink-replicate-region.ll22 ; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv>
110 ; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next>
117 ; CHECK-NEXT: WIDEN ir<%recur.next> = sext ir<%y>
131 ; CHECK-NEXT: REPLICATE ir<%add> = add ir<%rem>, ir<%recur.next>
133 ; CHECK-NEXT: REPLICATE store ir<%add>, ir<%gep>
185 ; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next>
186 ; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%and.red> = phi ir<1234>, ir<%and.red.next>
213 ; CHECK-NEXT: WIDEN ir<%and.red.next> = and ir<%and.red>, ir<%add>
262 ; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv>
358 ; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-ld1r.mir33 bb.0 (%ir-block.0):
47 ; CHECK: renamable $z0 = LD1RH_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object)
48 ; CHECK: renamable $z0 = LD1RH_S_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object)
49 ; CHECK: renamable $z0 = LD1RH_D_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object)
52 ; CHECK: renamable $z0 = LD1RW_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object)
53 ; CHECK: renamable $z0 = LD1RW_D_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object)
54 ; CHECK: renamable $z0 = LD1RSW_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object)
55 ; CHECK: renamable $z0 = LD1RD_IMM renamable $p0, $sp, 63 :: (load (s64) from %ir.object)
56 ; CHECK: renamable $z0 = LD1RD_IMM renamable $p0, $sp, 63 :: (load (s64) from %ir.object)
85 bb.0 (%ir-block.0):
[all …]
H A Dsve-ldnf1.mir40 bb.0 (%ir-block.0):
58 ; CHECK-NEXT: renamable $z0 = LDNF1H_IMM renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
59 ; CHECK-NEXT: renamable $z0 = LDNF1H_S_IMM renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
60 ; CHECK-NEXT: renamable $z0 = LDNF1H_D_IMM renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
61 … ; CHECK-NEXT: renamable $z0 = LDNF1SH_S_IMM renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
62 … ; CHECK-NEXT: renamable $z0 = LDNF1SH_D_IMM renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
66 ; CHECK-NEXT: renamable $z0 = LDNF1D_IMM renamable $p0, $sp, 7 :: (load (s64) from %ir.object)
99 bb.0 (%ir-block.0):
117 ; CHECK-NEXT: renamable $z0 = LDNF1H_IMM renamable $p0, $sp, -8 :: (load (s16) from %ir.object)
158 bb.0 (%ir-block.0):
[all …]
H A Dsve-ldstnt1.mir40 bb.0 (%ir-block.0):
52 ; CHECK-NEXT: renamable $z0 = LDNT1H_ZRI renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
54 ; CHECK-NEXT: renamable $z0 = LDNT1D_ZRI renamable $p0, $sp, 7 :: (load (s64) from %ir.object)
58 ; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, $sp, 7 :: (store (s64) into %ir.object)
83 bb.0 (%ir-block.0):
95 ; CHECK-NEXT: renamable $z0 = LDNT1H_ZRI renamable $p0, $sp, -8 :: (load (s16) from %ir.object)
96 ; CHECK-NEXT: renamable $z0 = LDNT1W_ZRI renamable $p0, $sp, -8 :: (load (s32) from %ir.object)
97 ; CHECK-NEXT: renamable $z0 = LDNT1D_ZRI renamable $p0, $sp, -8 :: (load (s64) from %ir.object)
101 ; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, $sp, -8 :: (store (s64) into %ir.object)
126 bb.0 (%ir-block.0):
[all …]
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dlvalue-bitcasts.cpp11 ir = reinterpret_cast<int&>(fr); in reinterpret_cast_test()
27 xr = reinterpret_cast<X&>(ir); in reinterpret_cast_test()
56 ir = (int&)fr; in c_cast()
60 ir = (int&)xr; in c_cast()
64 fr = (float&)ir; in c_cast()
72 xr = (X&)ir; in c_cast()
83 cfr = (_Complex float&)ir; in c_cast()
104 ir = intref(fr); in functional_cast()
108 ir = intref(xr); in functional_cast()
112 fr = floatref(ir); in functional_cast()
[all …]
/llvm-project-15.0.7/mlir/python/mlir/dialects/
H A D_ods_common.py122 return _cext.ir.Location.current.context
127 arg: _Union[_cext.ir.OpView, _cext.ir.Operation, _cext.ir.Value, _cext.ir.OpResultList]
128 ) -> _cext.ir.Value:
135 if isinstance(arg, _cext.ir.OpView):
137 elif isinstance(arg, _cext.ir.Operation):
142 assert isinstance(arg, _cext.ir.Value)
147 arg: _Union[_cext.ir.OpView, _cext.ir.Operation,
148 _Sequence[_Union[_cext.ir.OpView, _cext.ir.Operation, _cext.ir.Value]]]
149 ) -> _Union[_Sequence[_cext.ir.Value], _cext.ir.OpResultList]:
156 if isinstance(arg, _cext.ir.OpView):
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Demergency-spill.mir179 SD $at_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
180 SD $v0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
181 SD $v1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
182 SD $a0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
183 SD $a1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
184 SD $a2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
185 SD $a3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
186 SD $t0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
187 SD $t1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
188 SD $t2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
[all …]
/llvm-project-15.0.7/compiler-rt/test/profile/Posix/
H A Dinstrprof-value-prof-shared.test13 // RUN: env LLVM_PROFILE_FILE=%t.ir.profraw LLVM_VP_MAX_NUM_VALS_PER_SITE=255 %run %t.ir
14 // RUN: llvm-profdata merge -o %t.ir.profdata %t.ir.profraw
16 // RUN: llvm-profdata merge -text %t.ir.profdata -o %t.ir.proftxt
27 // RUN: llvm-profdata merge -o %t.ir.m.profdata %t.prof/
29 // RUN: llvm-profdata merge -text %t.ir.m.profdata -o %t.ir.m.proftxt
37 // RUN: env LLVM_PROFILE_FILE=%t.ir.dyn.profraw %run %t.ir.dyn
38 // RUN: llvm-profdata merge -o %t.ir.dyn.profdata %t.ir.dyn.profraw
40 // RUN: llvm-profdata merge -text %t.ir.dyn.profdata -o %t.ir.dyn.proftxt
47 // RUN: env LLVM_PROFILE_FILE=%t.ir.mixed.profraw LLVM_VP_MAX_NUM_VALS_PER_SITE=255 %run %t.ir.mix…
48 // RUN: llvm-profdata merge -o %t.ir.mixed.profdata %t.ir.mixed.profraw
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dfp-conv-17.mir127 bb.0 (%ir-block.0):
132 %2 = LE %1, 0, $noreg :: (volatile load (s32) from %ir.ptr2)
133 %3 = LE %1, 0, $noreg :: (volatile load (s32) from %ir.ptr2)
134 %4 = LE %1, 0, $noreg :: (volatile load (s32) from %ir.ptr2)
135 %5 = LE %1, 0, $noreg :: (volatile load (s32) from %ir.ptr2)
136 %6 = LE %1, 0, $noreg :: (volatile load (s32) from %ir.ptr2)
137 %7 = LE %1, 0, $noreg :: (volatile load (s32) from %ir.ptr2)
138 %8 = LE %1, 0, $noreg :: (volatile load (s32) from %ir.ptr2)
139 %9 = LE %1, 0, $noreg :: (volatile load (s32) from %ir.ptr2)
140 %10 = LE %1, 0, $noreg :: (volatile load (s32) from %ir.ptr2)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpr30821.mir72 …UPDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load (s128) from %ir.india)
94 …MOVAPDmr %stack.2.india, 1, $noreg, 0, $noreg, killed %13 :: (volatile store (s128) into %ir.india)
107 …MOVAPDmr %stack.2.india, 1, $noreg, 0, $noreg, killed %23 :: (volatile store (s128) into %ir.india)
118 … = VMOVSDrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.india)
120 VMOVSDmr %stack.2.india, 1, $noreg, 0, $noreg, killed %33 :: (store (s64) into %ir.india)
133 …2 = MOVSSrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.india)
135 VMOVSSZmr %stack.2.india, 1, $noreg, 0, $noreg, killed %43 :: (store (s32) into %ir.india)
146 …4 = MOVSDrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.india)
148 VMOVSDZmr %stack.2.india, 1, $noreg, 0, $noreg, killed %53 :: (store (s64) into %ir.india)
161 MOVSSmr %stack.2.india, 1, $noreg, 0, $noreg, killed %63 :: (store (s32) into %ir.india)
[all …]
/llvm-project-15.0.7/mlir/test/Integration/Dialect/SparseTensor/python/
H A Dtest_stress.py14 from mlir import ir
33 def __init__(self, context: ir.Context):
49 self._ir2sc = dict(( (ir,sc) for sc,ir in types_list ))
58 def sctype_to_irtype(self, sctype) -> ir.Type:
69 def irtype_to_sctype(self, tp: ir.Type):
80 return ir.RankedTensorType.get(nparray.shape,
101 def build(self, types: List[ir.Type]):
106 self._module = ir.Module.create()
107 with ir.InsertionPoint(self._module.body):
185 with ir.Context() as ctx, ir.Location.unknown():
[all …]
/llvm-project-15.0.7/compiler-rt/test/profile/
H A Dinstrprof-value-prof.test1 // RUN: rm -f %t.profraw %t.ir.profraw %t.ir.dyn.profraw
9 // RUN: env LLVM_PROFILE_FILE=%t.ir.profraw LLVM_VP_MAX_NUM_VALS_PER_SITE=255 %run %t.ir
10 // RUN: llvm-profdata merge -o %t.ir.profdata %t.ir.profraw
11 // RUN: llvm-profdata show --all-functions -ic-targets %t.ir.profdata | FileCheck %S/Inputs/instr…
12 // RUN: llvm-profdata merge -text %t.ir.profdata -o %t.ir.proftxt
13 // RUN: FileCheck %S/Inputs/instrprof-value-prof-real.c --check-prefix=IR < %t.ir.proftxt
17 // RUN: env LLVM_PROFILE_FILE=%t.ir.dyn.profraw %run %t.ir.dyn
18 // RUN: llvm-profdata merge -o %t.ir.dyn.profdata %t.ir.dyn.profraw
19 // RUN: llvm-profdata show --all-functions -ic-targets %t.ir.dyn.profdata | FileCheck %S/Inputs/i…
20 // RUN: llvm-profdata merge -text %t.ir.dyn.profdata -o %t.ir.dyn.proftxt
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Drem_and_div_vec.mir52 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
82 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
112 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
142 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
172 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
202 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
232 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
262 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
292 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
322 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
[all …]
H A Dfloating_point_vec_arithmetic_operations.mir41 %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
42 %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
44 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
71 %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
74 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
104 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
134 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
164 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
194 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
224 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Drem_and_div_vec.mir47 %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
48 %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
50 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
75 %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
76 %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
78 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
103 %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
104 %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
106 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
134 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
[all …]
H A Dfloating_point_vec_arithmetic_operations.mir39 %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
40 %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
42 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
67 %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
68 %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
70 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
95 %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
96 %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
98 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
126 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Drem_and_div_vec.mir48 %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
49 %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
51 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
77 %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
78 %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
80 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
106 %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
107 %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
109 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
138 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
[all …]
/llvm-project-15.0.7/mlir/test/python/ir/
H A Dcontext_lifecycle.py4 import mlir.ir
6 assert mlir.ir.Context._get_live_count() == 0
10 c1 = mlir.ir.Context()
11 assert mlir.ir.Context._get_live_count() == 1
18 assert mlir.ir.Context._get_live_count() == 1
25 c3 = mlir.ir.Context()
26 assert mlir.ir.Context._get_live_count() == 2
33 assert mlir.ir.Context._get_live_count() == 1
38 assert mlir.ir.Context._get_live_count() == 1
45 c4 = mlir.ir.Context()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dmake-compressible.mir317 SW $x0, killed renamable $x10, 0 :: (store (s32) into %ir.a)
318 SW $x0, killed renamable $x11, 0 :: (store (s32) into %ir.b)
319 SW $x0, killed renamable $x12, 0 :: (store (s32) into %ir.c)
433 ; RV32-NEXT: SW killed $x11, $x11, 0 :: (volatile store (s32) into %ir.q)
443 ; RV64-NEXT: SW killed $x11, $x11, 0 :: (volatile store (s32) into %ir.q)
550 ; RV32-NEXT: renamable $f10_f = FLW $x10, 0 :: (load (s32) from %ir.g)
561 renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g)
578 ; RV32-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
586 ; RV64-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
590 renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g)
[all …]
/llvm-project-15.0.7/mlir/test/Pass/
H A Dinvalid-ir-print-after-failure.mlir1 …peline='func.func(test-pass-create-invalid-ir{emit-invalid-ir=true signal-pass-failure=true})' -ml…
2 …peline='func.func(test-pass-create-invalid-ir{emit-invalid-ir=true signal-pass-failure=false})' -m…
3 …peline='func.func(test-pass-create-invalid-ir{emit-invalid-ir=false signal-pass-failure=true})' -m…
4 …eline='func.func(test-pass-create-invalid-ir{emit-invalid-ir=false signal-pass-failure=false})' -m…
7 …peline='func.func(test-pass-create-invalid-ir{emit-invalid-ir=true signal-pass-failure=true})' -ml…
8 …peline='func.func(test-pass-create-invalid-ir{emit-invalid-ir=true signal-pass-failure=false})' -m…
/llvm-project-15.0.7/lldb/test/Shell/Expr/
H A DTestIRMemoryMap.test5 # RUN: lldb-test ir-memory-map %t %S/Inputs/ir-memory-map-basic
6 # RUN: lldb-test ir-memory-map -host-only %t %S/Inputs/ir-memory-map-basic
8 # RUN: lldb-test ir-memory-map %t %S/Inputs/ir-memory-map-overlap1
9 # RUN: lldb-test ir-memory-map -host-only %t %S/Inputs/ir-memory-map-overlap1
11 # RUN: lldb-test ir-memory-map %t %S/Inputs/ir-memory-map-mix-malloc-free
12 # RUN: lldb-test ir-memory-map -host-only %t %S/Inputs/ir-memory-map-mix-malloc-free
H A DTestIRMemoryMapWindows.test6 # RUN: lldb-test ir-memory-map %t %S/Inputs/ir-memory-map-basic
7 # RUN: lldb-test ir-memory-map -host-only %t %S/Inputs/ir-memory-map-basic
9 # RUN: lldb-test ir-memory-map %t %S/Inputs/ir-memory-map-overlap1
10 # RUN: lldb-test ir-memory-map -host-only %t %S/Inputs/ir-memory-map-overlap1
12 # RUN: lldb-test ir-memory-map %t %S/Inputs/ir-memory-map-mix-malloc-free
13 # RUN: lldb-test ir-memory-map -host-only %t %S/Inputs/ir-memory-map-mix-malloc-free

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