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/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dset-nomacro.s3 # CHECK-NOT: warning: macro instruction expanded into multiple instructions
85 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
90 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
94 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
96 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
106 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
110 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
113 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
122 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
131 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
[all …]
H A Dset-nomacro-micromips.s7 # CHECK-NOT: warning: macro instruction expanded into multiple instructions
21 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
23 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
25 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
28 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
30 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
33 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dllc-start-stop-instance.ll23 ; STOP-AFTER-DEAD1: Remove dead machine instructions
24 ; STOP-AFTER-DEAD1: Remove dead machine instructions
30 ; STOP-AFTER-DEAD0-NOT: Remove dead machine instructions
31 ; STOP-AFTER-DEAD0: Remove dead machine instructions
32 ; STOP-AFTER-DEAD0-NOT: Remove dead machine instructions
37 ; STOP-BEFORE-DEAD1: Remove dead machine instructions
38 ; STOP-BEFORE-DEAD1-NOT: Remove dead machine instructions
43 ; START-BEFORE-DEAD1-NOT: Remove dead machine instructions
44 ; START-BEFORE-DEAD1: Remove dead machine instructions
45 ; START-BEFORE-DEAD1-NOT: Remove dead machine instructions
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKY.td73 "Support CSKY floate1 instructions">;
127 "Support CSKY dsp1e2 instructions">;
165 "Enable trust instructions">;
171 "Enable java instructions">;
189 "Enable doloop instructions">;
191 // Other features than instructions
208 "Enable vdsp-v2 instructions">;
270 "Support CSKY e1 instructions">;
277 "Support CSKY e2 instructions">;
283 "Support CSKY 2e3 instructions">;
[all …]
/llvm-project-15.0.7/llvm/docs/
H A DHowToUseInstrMappings.rst29 instructions with each other. These tables are emitted in the
36 // Used to reduce search space only to the instructions using this
42 // by all the instructions related by this relationship.
45 // List of fields/attributes that are same for all the instructions
77 // search space only to these set of instructions.
92 // are the instructions they (key) can transform into.
96 // instructions involved in this relationship model.
99 // The key column contains non-predicated instructions.
102 // Two value columns - first column contains instructions with
117 instructions:
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H A DAMDGPUInstructionSyntax.rst43 Most instructions which operate on packed data have a *_pk* suffix.
45 these instructions operate on and produce packed data composed of
64 There are instructions which have 2 type suffices:
110 Examples of instructions with different types of source and destination operands:
117 Examples of instructions with one data type:
124 Examples of instructions which operate with packed data:
132 Examples of typeless instructions which operate on b128 data:
144 Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
180 Information about modifiers supported for individual instructions may be found in GPU-specific docu…
/llvm-project-15.0.7/bolt/test/X86/
H A Djump-table-icp.test31 CHECK: .LBB{{.*}} (8 instructions, align : 1)
36 CHECK: .LFT{{.*}} (4 instructions, align : 1)
41 CHECK: .Ltmp{{.*}} (1 instructions, align : 1)
46 CHECK: .Ltmp{{.*}} (5 instructions, align : 1)
50 CHECK: .Ltmp{{.*}} (5 instructions, align : 1)
54 CHECK: .Ltmp{{.*}} (5 instructions, align : 1)
58 CHECK: .Ltmp{{.*}} (5 instructions, align : 1)
62 CHECK: .Ltmp{{.*}} (5 instructions, align : 1)
67 CHECK: .LBB{{.*}} (8 instructions, align : 1)
72 CHECK: .LFT{{.*}} (4 instructions, align : 1)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/IROutliner/
H A Dopt-remarks.ll39 ; YAML-NEXT: - String: ' instructions at locations '
53 ; YAML-NEXT: - String: ' instructions at locations '
67 ; YAML-NEXT: - String: ' instructions at locations '
81 ; YAML-NEXT: - String: ' instructions at locations '
95 ; YAML-NEXT: - String: ' instructions at locations '
109 ; YAML-NEXT: - String: ' instructions at locations '
123 ; YAML-NEXT: - String: ' instructions at locations '
137 ; YAML-NEXT: - String: ' instructions at locations '
151 ; YAML-NEXT: - String: ' instructions at locations '
165 ; YAML-NEXT: - String: ' instructions at locations '
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPC.td65 "Enable floating-point instructions">;
77 "Enable SPE instructions",
143 "Enable VSX instructions",
159 "Enable Power8 direct move instructions",
266 def FeatureISAFuture : SubtargetFeature<"isa-future-instructions",
299 "32Byte load and store instructions",
302 "Enable MMA instructions",
311 "Add privileged instructions">;
475 // The key column are the non-record-form instructions.
488 // The key column are the record-form instructions.
[all …]
H A DP10InstrResources.td20 // 2-way crack instructions
40 // 2-way crack instructions
61 // 2-way crack instructions
76 // 2-way crack instructions
249 // 2-way crack instructions
256 // 2-way crack instructions
1378 // Expand instructions
1385 // Expand instructions
1916 // Expand instructions
1932 // Expand instructions
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARM.td148 // True if the subtarget supports CLREX instructions.
200 // True if processor supports CRC instructions.
347 // True if VFP instructions are not pipelined.
355 // If the VFP2 / NEON instructions are available, indicates
394 /// True if codegen would avoid using instructions
423 // instructions.
461 // Generate calls via indirect call instructions.
584 // True if Thumb2 instructions are supported.
606 "v5TExp instructions",
693 "Support ARM v8-1M Mainline instructions",
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagon.td31 "Hexagon ZReg extension instructions">;
33 "true", "Hexagon HVX QFloating point instructions">;
36 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
38 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
41 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
44 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
47 "Hexagon::ArchEnum::V66", "Hexagon HVX instructions",
68 "Hexagon Audio extension instructions">;
74 "Use compound instructions">;
84 "Use memop instructions">;
[all …]
/llvm-project-15.0.7/lldb/examples/python/
H A Dgdb_disassemble.py6 instructions = lldb.frame.function.instructions
10 instructions = lldb.frame.symbol.instructions
14 for inst in instructions:
/llvm-project-15.0.7/lldb/docs/use/
H A Dintel_pt.rst8 tracing of all the instructions executed by a process.
78 > thread trace dump instructions
81 thread #2: tid = 2861133, total instructions = 5305673
112 Printing more instructions
119 thread trace dump instructions -c <count>
121 Printing the instructions of another thread
129 thread trace dump instructions <#thread index>
131 thread trace dump instructions 8
143 thread trace dump instructions
157 (lldb) thread trace dump instructions -c 5
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/llvm-project-15.0.7/llvm/docs/HistoricalNotes/
H A D2002-05-12-InstListChange.txt12 instructions. To iterate over instructions, we must actually iterate over
13 the instlist, and access the instructions through the instlist.
22 instructions.
24 Additionally, adding or removing instructions to a basic block
29 the instructions be represented with a doubly linked list in the
30 instructions themselves, instead of an external data structure. This is
40 Iteration over the instructions in a basic block remains the simple:
46 After converting instructions over, I'll convert basic blocks and
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedPredExynos.td16 // Check the shift in arithmetic and logic instructions.
32 // Identify arithmetic instructions without or with limited extension or shift.
60 // Identify logic instructions with limited shift.
76 // Identify more logic instructions with limited shift.
111 // Identify FP instructions.
114 // Identify 128-bit NEON instructions.
117 // Identify instructions that reset a register efficiently.
145 // Identify cheap arithmetic and logic immediate instructions.
H A DAArch64SchedPredicates.td16 // Check the extension type in arithmetic instructions.
28 // Check for shifting in extended arithmetic instructions.
74 // Identify arithmetic instructions with extend.
80 // Identify arithmetic immediate instructions.
84 // Identify arithmetic instructions with shift.
88 // Identify arithmetic instructions without shift.
92 // Identify logic immediate instructions.
97 // Identify logic instructions with shift.
105 // Identify logic instructions without shift.
113 // Identify arithmetic and logic immediate instructions.
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFormats.td27 // When there are multiple instructions that map to the same encoding (in
32 // Normal instructions. Default instantiation of a WebAssemblyInst.
48 // instructions are used for ISel and all MI passes. The stack versions of the
49 // instructions do not have register operands (they implicitly operate on the
50 // stack), and local.gets and local.sets are explicit. The register instructions
51 // are converted to their corresponding stack instructions before lowering to
54 // there is always an equivalent pair of instructions.
64 // For instructions that have no register ops, so both sets are the same.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86.td70 "Enable SSE instructions">;
72 "Enable SSE2 instructions",
75 "Enable SSE3 instructions",
111 "Enable AVX instructions",
363 "instructions into a POP+LFENCE+JMP sequence.">;
562 // rotate instructions.
569 // instructions) with conditional branches.
591 "Prefer 128-bit AVX instructions">;
595 "Prefer 256-bit AVX instructions">;
612 "normal vector instructions with shuffles">;
[all …]
H A DX86InstrFormats.td302 // Attributes specific to X86 instructions...
504 // SI - SSE 1 & 2 scalar instructions
552 // PI - SSE 1 & 2 packed instructions
592 // SSI - SSE1 instructions with XS prefix.
593 // PSI - SSE1 instructions with PS prefix.
688 // S3SI - SSE3 instructions with XS prefix.
689 // S3DI - SSE3 instructions with XD prefix.
761 // CRC32I - SSE 4.2 CRC32 instructions.
995 // MMXI - MMX instructions with TB prefix.
1001 // MMXID - MMX instructions with XD prefix.
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/ELF/ARM/
H A Dliteral-vldr-thumb2.s16 @@ Check AddrMode5 instructions, with positive and negative immediates
23 @@ Same instructions, but the addresses are not 4-byte aligned
30 @@ Check that AddrMode5 instructions which do not use PC-relative addressing are not annotated
34 @@ Check AddrMode5FP16 instructions, with positive and negative immediates
45 @@ Same instructions, but the addresses are not 4-byte aligned
56 @@ Check that AddrMode5FP16 instructions which do not use PC-relative addressing are not annotated
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dverify-ds-gws-align.mir3 … *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
5 … *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
7 … *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
9 … *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
11 … *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
13 … *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
15 … *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
/llvm-project-15.0.7/llvm/bindings/python/llvm/tests/
H A Dtest_disassembler.py30 instructions = list(disassembler.get_instructions(sequence))
31 self.assertEqual(len(instructions), 2)
33 self.assertEqual(instructions[0], (0, 3, '\tjcxz\t-127'))
34 self.assertEqual(instructions[1], (3, 2, '\taddl\t%eax, %edi'))
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td56 "Most fp64 instructions are full rate"
301 "Additional instructions for CI+"
367 "Has i16/f16 instructions"
373 "True 16-bit operand instructions"
379 "Has VOP3P packed instructions"
385 "Has v_movrel*_b32 instructions"
494 "Support image instructions"
585 "Has mAI instructions"
591 "Has fp8 and bf8 instructions"
676 "Has ds_*_src2 instructions"
[all …]
/llvm-project-15.0.7/mlir/utils/spirv/
H A Dgen_spirv_dialect.py428 def gen_opcode(instructions): argument
435 max_len = max([len(inst['opname']) for inst in instructions])
462 def map_cap_to_opnames(instructions): argument
473 for inst in instructions:
482 def gen_instr_coverage_report(path, instructions): argument
497 instructions))
499 instructions_opnames = [inst['opname'] for inst in instructions]
504 instructions))
532 def update_td_opcodes(path, instructions, filter_list): argument
923 def update_td_op_definitions(path, instructions, docs, filter_list, argument
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