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Searched refs:imm5 (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h24 static inline uint32_t DecodeImmShift(const uint32_t type, const uint32_t imm5, in DecodeImmShift() argument
31 return imm5; in DecodeImmShift()
34 return (imm5 == 0 ? 32 : imm5); in DecodeImmShift()
37 return (imm5 == 0 ? 32 : imm5); in DecodeImmShift()
39 if (imm5 == 0) { in DecodeImmShift()
44 return imm5; in DecodeImmShift()
68 const uint32_t imm5) { in DecodeImmShift() argument
70 return DecodeImmShift(shift_t, imm5, dont_care); in DecodeImmShift()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td138 !strconcat(opstr, "\t$rz, $imm5"), []> {
140 bits<5> imm5;
145 let Inst{4 - 0} = imm5;
149 AddrModeNone, (outs CARRY:$ca), (ins mGPR:$rx, Immoperand:$imm5),
150 !strconcat(opstr, "\t$rx, $imm5"), []> {
152 bits<5> imm5;
157 let Inst{4 - 0} = imm5;
173 AddrModeNone, (outs mGPR:$rz), (ins mGPR:$rx, uimm5:$imm5),
174 !strconcat(opstr, "\t$rz, $rx, $imm5"), [(set mGPR:$rz, (opnode mGPR:$rx, uimm5:$imm5))]> {
177 bits<5> imm5;
[all …]
H A DCSKYInstrFormats.td271 bits<5> imm5;
276 let Inst{4 - 0} = imm5;
287 bits<5> imm5;
290 let Inst{25 - 21} = imm5;
397 let Inst{4 - 0} = regs{4 - 0}; // imm5
476 bits<5> imm5;
478 let Inst{25 - 21} = imm5;
492 bits<5> imm5;
494 let Inst{25 - 21} = imm5;
505 bits<5> imm5;
[all …]
H A DCSKYInstrInfo.td478 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
479 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
481 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
482 [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
484 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
485 [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
487 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
488 [(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;
491 "rotri32 $rz, $rx, $imm5", []>;
888 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5), []>;
[all …]
H A DCSKYInstrInfo16Instr.td159 def CMPLEI16 : CSKYPseudo<(outs CARRY:$ca), (ins mGPR:$rx, uimm5:$imm5),
160 "cmplei16\t$rx, $imm5", []>;
310 def BCLRI16 : I16_Z_5<0b100, (outs mGPR:$rz), (ins mGPR:$rZ, uimm5:$imm5),
312 def BSETI16 : I16_Z_5<0b101, (outs mGPR:$rz), (ins mGPR:$rZ, uimm5:$imm5),
317 def BTSTI16 : I16_Z_5<0b110, (outs CARRY:$ca), (ins mGPR:$rz, uimm5:$imm5),
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrFormats.td112 bits<5> imm5;
117 let Inst{14-10} = imm5;
303 bits<5> imm5;
308 let Inst{4-0} = imm5;
318 bits<5> imm5;
323 let Inst{4-0} = imm5;
H A DLoongArchInstrInfo.td215 : Fmt2RI5<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm5), opstr,
216 "$rd, $rj, $imm5">;
391 def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12), "preld",
392 "$imm5, $rj, $imm12">;
490 def PRELDX : FmtPRELDX<(outs), (ins uimm5:$imm5, GPR:$rj, GPR:$rk), "preldx",
491 "$imm5, $rj, $rk">;
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/
H A Dmisc.mir171 # opcode | imm12 | rj | imm5
190 # opcode | rk | rj | imm5
H A D2ri.mir13 # opcode | imm5 | rj | rd
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrThumb.td263 // t_addrmode_is1 := reg + imm5
716 // Loads: reg/reg and reg/imm5
726 def i : // reg/imm5
738 // Stores: reg/reg and reg/imm5
744 def i : // reg/imm5
1083 bits<5> imm5;
1084 let Inst{10-6} = imm5;
1168 bits<5> imm5;
1169 let Inst{10-6} = imm5;
1186 bits<5> imm5;
[all …]
H A DARMInstrFormats.td1321 let Inst{10-6} = addr{7-3}; // imm5
H A DARMInstrInfo.td744 // {4-0} imm5 shift amount.
745 // asr #32 encoded as imm5 == 0.
H A DARMInstrThumb2.td35 // {4-0} imm5 shift amount.
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dunpredictable-MVN-arm.txt8 # | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | imm5 |type | 0| Rm |
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2433 // [45] "cmpeq $Pd, $Pg/z, $Zn, $imm5";
2439 // [47] "cmpge $Pd, $Pg/z, $Zn, $imm5";
2445 // [49] "cmpgt $Pd, $Pg/z, $Zn, $imm5";
2463 // [55] "cmple $Pd, $Pg/z, $Zn, $imm5";
2481 // [61] "cmplt $Pd, $Pg/z, $Zn, $imm5";
2487 // [63] "cmpne $Pd, $Pg/z, $Zn, $imm5";
2867 // [190] "index $Zd, $Rn, $imm5";
2870 // [191] "index $Zd, $imm5, $Rm";
2873 // [192] "index $Zd, $imm5, $imm5b";
3562 // [423] "st1b $Zt, $Pg, [$Zn, $imm5]";
[all …]
H A DSVEInstrFormats.td4825 bits<5> imm5;
4829 let Inst{20-16} = imm5;
5237 bits<5> imm5;
5244 let Inst{9-5} = imm5;
5283 bits<5> imm5;
5350 bits<5> imm5;
6100 bits<5> imm5;
7174 bits<5> imm5;
7310 bits<5> imm5;
7579 bits<5> imm5;
[all …]
H A DAArch64InstrFormats.td7341 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
7347 let Inst{20-16} = imm5;
/llvm-project-15.0.7/lld/ELF/Arch/
H A DRISCV.cpp318 uint16_t imm5 = extractBits(val, 5, 5) << 2; in relocate() local
319 insn |= imm8 | imm4_3 | imm7_6 | imm2_1 | imm5; in relocate()
336 uint16_t imm5 = extractBits(val, 5, 5) << 2; in relocate() local
337 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; in relocate()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dconstants-i64.ll221 define i64 @imm5() #0 {
222 ; CHECK-LABEL: imm5:
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips16InstrFormats.td228 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
237 bits<5> imm5;
244 let Inst{4-0} = imm5;
H A DMips64InstrInfo.td926 def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))),
928 (SLL GPR32:$src, immZExt5:$imm5), sub_32)>;
932 def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))),
934 (SRL GPR32:$src, immZExt5:$imm5), sub_32)>;
938 def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))),
940 (SRA GPR32:$src, immZExt5:$imm5), sub_32)>;
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/MIPS/
H A DEmulateInstructionMIPS.cpp1490 uint32_t imm5 = insn.getOperand(2).getImm(); in Emulate_SWSP() local
1511 address = address + imm5; in Emulate_SWSP()
1634 uint32_t imm5 = insn.getOperand(2).getImm(); in Emulate_LWSP() local
1648 base_address = base_address + imm5; in Emulate_LWSP()
1740 int32_t imm5 = insn.getOperand(0).getImm(); in Emulate_JRADDIUSP() local
1759 int32_t result = src_opd_val + imm5; in Emulate_JRADDIUSP()
1770 context.SetRegisterPlusOffset(reg_info_sp, imm5); in Emulate_JRADDIUSP()
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp3756 uint32_t imm5; // encoding for the shift amount in EmulateShiftImm() local
3779 imm5 = Bits32(opcode, 10, 6); in EmulateShiftImm()
3790 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6); in EmulateShiftImm()
3798 imm5 = Bits32(opcode, 11, 7); in EmulateShiftImm()
3805 if (shift_type == SRType_ROR && imm5 == 0) in EmulateShiftImm()
5384 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateSTRRegister() local
5385 shift_n = DecodeImmShift(typ, imm5, shift_t); in EmulateSTRRegister()
6576 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateLDRRegister() local
6577 shift_n = DecodeImmShift(type, imm5, shift_t); in EmulateLDRRegister()
7000 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateLDRBRegister() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVVLPatterns.td1200 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), (ImmPat XLenVT:$imm5),
1203 XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>;
1204 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, (ImmPat XLenVT:$imm5),
1207 $passthru, XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>;