Lines Matching refs:imm5
239 // t_addrmode_is4 := reg + imm5 * 4
251 // t_addrmode_is2 := reg + imm5 * 2
263 // t_addrmode_is1 := reg + imm5
716 // Loads: reg/reg and reg/imm5
726 def i : // reg/imm5
738 // Stores: reg/reg and reg/imm5
744 def i : // reg/imm5
1078 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1080 "asr", "\t$Rd, $Rm, $imm5",
1081 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1083 bits<5> imm5;
1084 let Inst{10-6} = imm5;
1163 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
1165 "lsl", "\t$Rd, $Rm, $imm5",
1166 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
1168 bits<5> imm5;
1169 let Inst{10-6} = imm5;
1181 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1183 "lsr", "\t$Rd, $Rm, $imm5",
1184 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1186 bits<5> imm5;
1187 let Inst{10-6} = imm5;
1395 def tLSLSri : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, imm0_31:$imm5),
1397 [(set tGPR:$Rd, CPSR, (ARMlsls tGPR:$Rn, imm0_31:$imm5))]>,