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/llvm-project-15.0.7/llvm/test/Analysis/DemandedBits/
H A Dintrinsics.ll27 declare i33 @llvm.fshr.i33(i33, i33, i33)
43 ; CHECK-DAG: DemandedBits: 0xffff for %z = call i33 @llvm.fshr.i33(i33 %x2, i33 %y2, i33 25)
45 define i33 @test_fshr(i33 %x, i33 %y) {
48 %z = call i33 @llvm.fshr.i33(i33 %x2, i33 %y2, i33 25)
50 ret i33 %r
67 ; CHECK-DAG: DemandedBits: 0xffff for %z = call i33 @llvm.fshr.i33(i33 %x2, i33 %y2, i33 33)
69 define i33 @test_fshr_full_shift(i33 %x, i33 %y) {
72 %z = call i33 @llvm.fshr.i33(i33 %x2, i33 %y2, i33 33)
94 ; CHECK-DAG: DemandedBits: 0xffff for %f = call i33 @llvm.fshr.i33(i33 %x2, i33 %y2, i33 %z2)
96 define i33 @test_fshr_non_pow2_bitwidth(i33 %x, i33 %y, i33 %z) {
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/
H A Dbitcount.ll6 declare i33 @llvm.ctlz.i33(i33 %val, i1)
31 %x = call i33 @llvm.ctlz.i33(i33 87359874, i1 true)
63 %x = call i33 @llvm.ctlz.i33(i33 0, i1 false)
71 %x = call i33 @llvm.ctlz.i33(i33 0, i1 true)
103 %x = call i33 @llvm.ctlz.i33(i33 undef, i1 false)
111 %x = call i33 @llvm.ctlz.i33(i33 undef, i1 true)
157 ; CHECK-NEXT: ret <2 x i33> <i33 25, i33 28>
159 %x = call <2 x i33> @llvm.ctlz.v2i33(<2 x i33> <i33 255, i33 16>, i1 true)
165 ; CHECK-NEXT: ret <2 x i33> <i33 33, i33 0>
167 %x = call <2 x i33> @llvm.ctlz.v2i33(<2 x i33> <i33 0, i33 undef>, i1 false)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfsh.ll7 declare i33 @llvm.fshr.i33(i33, i33, i33)
57 %r = call i33 @llvm.fshr.i33(i33 %x, i33 %y, i33 %maskedsh)
83 %r = call i33 @llvm.fshr.i33(i33 %x, i33 %y, i33 %maskedsh)
175 %r = call i33 @llvm.fshr.i33(i33 undef, i33 %x, i33 7)
184 %r = call i33 @llvm.fshr.i33(i33 0, i33 %x, i33 7)
211 %r = call i33 @llvm.fshr.i33(i33 %x, i33 undef, i33 7)
220 %r = call i33 @llvm.fshr.i33(i33 %x, i33 0, i33 7)
326 %z = call i33 @llvm.fshr.i33(i33 %x, i33 %y, i33 7)
337 %z = call i33 @llvm.fshr.i33(i33 %x, i33 %y, i33 7)
367 %r = call i33 @llvm.fshr.i33(i33 %x, i33 %y, i33 34)
[all …]
H A Dcmp-intrinsic.ll7 declare i33 @llvm.cttz.i33(i33, i1)
251 %tz = tail call i33 @llvm.cttz.i33(i33 %x, i1 false)
272 %tz = tail call i33 @llvm.cttz.i33(i33 %x, i1 false)
293 %tz = tail call i33 @llvm.cttz.i33(i33 %x, i1 false)
314 %tz = tail call i33 @llvm.cttz.i33(i33 %x, i1 false)
337 %tz = tail call i33 @llvm.cttz.i33(i33 %x, i1 false)
338 store i33 %tz, i33* %p
349 %tz = tail call i33 @llvm.cttz.i33(i33 %x, i1 false)
360 %tz = tail call i33 @llvm.cttz.i33(i33 %x, i1 false)
371 %tz = tail call i33 @llvm.cttz.i33(i33 %x, i1 false)
[all …]
H A Dmul-masked-bits.ll113 define i33 @squared_one_demanded_low_bit(i33 %x) {
118 %mul = mul i33 %x, %x
119 %and = and i33 %mul, 1
120 ret i33 %and
133 define i33 @squared_demanded_2_low_bits(i33 %x) {
138 %mul = mul i33 %x, %x
139 %and = and i33 %mul, 3
140 ret i33 %and
156 define i33 @squared_demanded_3_low_bits(i33 %x) {
162 %mul = mul i33 %x, %x
[all …]
H A Dapint-and-compare.ll4 define i1 @test1(i33 %a, i33 %b) {
5 %tmp1 = and i33 %a, 65280
6 %tmp3 = and i33 %b, 65280
7 %tmp = icmp ne i33 %tmp1, %tmp3
H A Dapint-not.ll6 define i33 @test1(i33 %A) {
7 %B = xor i33 %A, -1
8 %C = xor i33 %B, -1
9 ret i33 %C
H A Dapint-div1.ll7 define i33 @test1(i33 %X) {
8 %Y = udiv i33 %X, 4096
9 ret i33 %Y
H A Dapint-rem1.ll7 define i33 @test1(i33 %A) {
8 %B = urem i33 %A, 4096
9 ret i33 %B
H A Dshift-shift.ll91 define <2 x i33> @shl_shl_splat_vec(<2 x i33> %A) {
95 %B = shl <2 x i33> %A, <i33 5, i33 5>
96 %C = shl <2 x i33> %B, <i33 28, i33 28>
97 ret <2 x i33> %C
102 define <2 x i33> @shl_shl_vec(<2 x i33> %A) {
104 ; CHECK-NEXT: [[B:%.*]] = shl <2 x i33> [[A:%.*]], <i33 6, i33 5>
105 ; CHECK-NEXT: [[C:%.*]] = shl <2 x i33> [[B]], <i33 27, i33 28>
106 ; CHECK-NEXT: ret <2 x i33> [[C]]
108 %B = shl <2 x i33> %A, <i33 6, i33 5>
109 %C = shl <2 x i33> %B, <i33 27, i33 28>
[all …]
H A Dminmax-fold.ll1079 define <2 x i33> @add_umax_vec(<2 x i33> %x) {
1081 ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i33> @llvm.umax.v2i33(<2 x i33> [[X:%.*]], <2 x i33> <i33…
1082 ; CHECK-NEXT: [[TMP2:%.*]] = add nuw <2 x i33> [[TMP1]], <i33 5, i33 5>
1085 %a = add nuw <2 x i33> %x, <i33 5, i33 5>
1086 %c = icmp ugt <2 x i33> %a, <i33 240, i33 240>
1087 %r = select <2 x i1> %c, <2 x i33> %a, <2 x i33> <i33 240, i33 240>
1324 ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i33> @llvm.smax.v2i33(<2 x i33> [[X:%.*]], <2 x i33> <i33…
1325 ; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw <2 x i33> [[TMP1]], <i33 5, i33 5>
1328 %a = add nsw <2 x i33> %x, <i33 5, i33 5>
1329 %c = icmp sgt <2 x i33> %a, <i33 240, i33 240>
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/ValueTracking/
H A Dknownzero-shift.ll33 define <2 x i33> @shl_shl_splat_vec(<2 x i33> %A) {
35 ; CHECK-NEXT: [[B:%.*]] = shl <2 x i33> [[A:%.*]], <i33 5, i33 5>
36 ; CHECK-NEXT: [[C:%.*]] = shl <2 x i33> [[B]], <i33 28, i33 28>
39 %B = shl <2 x i33> %A, <i33 5, i33 5>
40 %C = shl <2 x i33> %B, <i33 28, i33 28>
41 ret <2 x i33> %C
46 define <2 x i33> @shl_shl_vec(<2 x i33> %A) {
48 ; CHECK-NEXT: [[B:%.*]] = shl <2 x i33> [[A:%.*]], <i33 6, i33 5>
49 ; CHECK-NEXT: [[C:%.*]] = shl <2 x i33> [[B]], <i33 27, i33 28>
52 %B = shl <2 x i33> %A, <i33 6, i33 5>
[all …]
/llvm-project-15.0.7/llvm/test/Integer/
H A Dconstexpr_bt.ll18 @t3 = global i33* bitcast (i33* @t1 to i33*) ;; Forward reference with cast
19 @t1 = global i33 4 ;; i32* @0
20 @t4 = global i33** bitcast (i33** @t3 to i33**) ;; Cast of a previous cast
22 @t6 = global i33*** @t4
24 @t9 = global i33 fptosi (float sitofp (i33 8 to float) to i33) ;; Nested cast expression
36 @array = constant [2 x i33] [ i33 12, i33 52 ]
37 @arrayPtr = global i33* getelementptr ([2 x i33], [2 x i33]* @array, i64 0, i64 0) ;; i33* &@arr…
38 @arrayPtr5 = global i33** getelementptr (i33*, i33** @arrayPtr, i64 5) ;; i33* &@arrayPtr[5]
44 @char8a = global i33* bitcast (i8* getelementptr([11x i8], [11x i8]* @somestr, i64 0, i64 8) to i33…
53 %SType = type { i33 , {float, {i8} }, i64 } ;; struct containing struct
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Dfshl.ll7 define i33 @fshr_multi_use(i33 %a) {
17 %b = tail call i33 @llvm.fshr.i33(i33 %a, i33 %a, i33 1)
18 %e = and i33 %b, 31
19 ret i33 %e
22 declare i33 @llvm.fshr.i33(i33, i33, i33)
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmax3.ll195 %a = load i33, i33 addrspace(1)* %gep0
196 %b = load i33, i33 addrspace(1)* %gep1
197 %c = load i33, i33 addrspace(1)* %gep2
199 %i0 = select i1 %icmp0, i33 %a, i33 %b
201 %i1 = select i1 %icmp1, i33 %i0, i33 %c
202 store i33 %i1, i33 addrspace(1)* %out
214 %a = load i33, i33 addrspace(1)* %gep0
215 %b = load i33, i33 addrspace(1)* %gep1
216 %c = load i33, i33 addrspace(1)* %gep2
218 %i0 = select i1 %icmp0, i33 %a, i33 %b
[all …]
H A Damdgpu-codegenprepare-mul24.ll586 define i33 @smul24_i33(i33 %lhs, i33 %rhs) {
635 define i33 @umul24_i33(i33 %lhs, i33 %rhs) {
734 define <2 x i33> @smul24_v2i33(<2 x i33> %lhs, <2 x i33> %rhs) {
737 ; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9>
739 ; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[SHL_RHS]], <i33 9, i33 9>
768 ; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9>
770 ; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[SHL_RHS]], <i33 9, i33 9>
805 %shl.lhs = shl <2 x i33> %lhs, <i33 9, i33 9>
806 %lhs24 = ashr <2 x i33> %shl.lhs, <i33 9, i33 9>
807 %shl.rhs = shl <2 x i33> %rhs, <i33 9, i33 9>
[all …]
H A Dmin3.ll265 %a = load i33, i33 addrspace(1)* %gep0
266 %b = load i33, i33 addrspace(1)* %gep1
267 %c = load i33, i33 addrspace(1)* %gep2
269 %i0 = select i1 %icmp0, i33 %a, i33 %b
271 %i1 = select i1 %icmp1, i33 %i0, i33 %c
272 store i33 %i1, i33 addrspace(1)* %outgep
284 %a = load i33, i33 addrspace(1)* %gep0
285 %b = load i33, i33 addrspace(1)* %gep1
286 %c = load i33, i33 addrspace(1)* %gep2
288 %i0 = select i1 %icmp0, i33 %a, i33 %b
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Drv64i-w-insts-legalization.ll34 %4 = zext i32 %1 to i33
37 %7 = zext i32 %6 to i33
38 %8 = mul i33 %4, %7
39 %9 = lshr i33 %8, 1
40 %10 = trunc i33 %9 to i32
79 %4 = zext i32 %1 to i33
82 %7 = zext i32 %6 to i33
83 %8 = mul i33 %4, %7
84 %9 = lshr i33 %8, 1
85 %10 = trunc i33 %9 to i32
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/
H A Dnonlinear-postinc.ll20 %t18 = zext i32 %t2 to i33
22 %t20 = zext i32 %t19 to i33
23 %t21 = mul i33 %t18, %t20
24 %t22 = lshr i33 %t21, 1
25 %t23 = trunc i33 %t22 to i32
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dnontemporal-load-store.ll119 define void @test_i33_store(i33* nocapture %ddst) {
129 %ddst.addr = phi i33* [ %ddst, %entry ], [ %incdec.ptr3, %for.body ]
130 %incdec.ptr = getelementptr inbounds i33, i33* %ddst.addr, i64 1
131 store i33 10, i33* %ddst.addr, align 4, !nontemporal !8
132 %incdec.ptr1 = getelementptr inbounds i33, i33* %ddst.addr, i64 2
133 store i33 20, i33* %incdec.ptr, align 4, !nontemporal !8
134 %incdec.ptr2 = getelementptr inbounds i33, i33* %ddst.addr, i64 3
135 store i33 30, i33* %incdec.ptr1, align 4, !nontemporal !8
136 %incdec.ptr3 = getelementptr inbounds i33, i33* %ddst.addr, i64 4
137 store i33 40, i33* %incdec.ptr2, align 4, !nontemporal !8
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsrem-seteq-illegal-types.ll57 define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
106 %srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
107 %cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3>
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dsrem-seteq-illegal-types.ll61 define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
141 %srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
142 %cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3>
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dsrem-seteq-illegal-types.ll77 define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
136 %srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
137 %cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3>
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dcall.ll1387 declare <3 x i33> @llvm.ctpop.v3i33(<3 x i33>)
1414 define <3 x i33> @ctpop_signbit(<3 x i33> %x) {
1416 ; CHECK-NEXT: [[B:%.*]] = lshr <3 x i33> [[X:%.*]], <i33 32, i33 32, i33 32>
1419 %b = lshr <3 x i33> %x, <i33 32, i33 32, i33 32>
1428 ; CHECK-NEXT: [[B:%.*]] = lshr <3 x i33> [[X:%.*]], <i33 31, i33 31, i33 31>
1432 %b = lshr <3 x i33> %x, <i33 31, i33 31, i33 31>
1446 declare <3 x i33> @llvm.cttz.v3i33(<3 x i33>, i1)
1457 define <3 x i33> @cttz_shl1_vec(<3 x i33> %x) {
1461 %s = shl <3 x i33> <i33 1, i33 1, i33 undef>, %x
1504 %s = lshr <3 x i33> <i33 undef, i33 4294967296, i33 4294967296>, %x
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dsrem-seteq-illegal-types.ll120 define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
249 %srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
250 %cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3>

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