Searched refs:hasV6Ops (Results 1 – 11 of 11) sorted by relevance
142 return hasV6Ops() && hasARMOps() && !isTargetWindows(); in isXRaySupported()444 if (!hasV6Ops()) in useFastISel()
17 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,19 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
50 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) in copyPhysReg()
340 return HasDataBarrier || (hasV6Ops() && !isThumb()); in hasAnyDataBarrier()
2685 bool hasV6Ops = Subtarget->hasV6Ops(); in ARMEmitIntExt() local2689 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt]; in ARMEmitIntExt()
1200 if (!Subtarget->hasV6Ops()) in ARMTargetLowering()1386 if (!Subtarget->hasV6Ops()) { in ARMTargetLowering()1570 if (Subtarget->hasV6Ops()) in ARMTargetLowering()5025 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) in LowerADDSUBSAT()12839 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) in AddCombineTo64bitUMAAL()14223 if (!Subtarget->hasV6Ops() || in PerformORCombineToSMULWBT()20020 if (!Subtarget->hasV6Ops()) in ExpandInlineAsm()21024 has64BitAtomicStore = Subtarget->hasV6Ops(); in shouldExpandAtomicStoreInIR()21046 has64BitAtomicLoad = Subtarget->hasV6Ops(); in shouldExpandAtomicLoadInIR()21067 hasAtomicRMW = Subtarget->hasV6Ops(); in shouldExpandAtomicRMWInIR()[all …]
741 !STI->hasV6Ops()) { in CreateLoadStoreMulti()2294 STI->hasV6Ops() ? TD->getABITypeAlign(Type::getInt64Ty(Func.getContext())) in CanFormLdStDWord()
3930 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()3949 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()3955 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) in Select()
435 if (Inst && ((ST->hasV6Ops() && !ST->isThumb()) || ST->isThumb2()) && in getIntImmCostInst()
4841 if (MI.getOpcode() == ARM::tMOVr && !Subtarget.hasV6Ops()) { in verifyInstruction()
539 bool hasV6Ops() const { in hasV6Ops() function in __anon2aa686d00111::ARMAsmParser10763 else if (Opc == ARM::tMOVr && !hasV6Ops() && in checkTargetMatchPredicate()