1150   if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()  in ARMTargetLowering()
1200   if (!Subtarget->hasV6Ops())  in ARMTargetLowering()
1361       (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {  in ARMTargetLowering()
1386   if (!Subtarget->hasV6Ops()) {  in ARMTargetLowering()
1570   if (Subtarget->hasV6Ops())  in ARMTargetLowering()
1575   if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) ||  in ARMTargetLowering()
1928       (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? Align(8) : Align(4));  in shouldAlignPointerArgs()
4210     assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&  in LowerATOMIC_FENCE()
5025   if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())  in LowerADDSUBSAT()
5376   if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())  in LowerSELECT_CC()
12792   if (Subtarget->hasV6Ops() && Subtarget->hasDSP() && Subtarget->useMulOps() &&  in AddCombineTo64bitMLAL()
12839   if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())  in AddCombineTo64bitUMAAL()
12887   if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())  in PerformUMLALCombine()
14223   if (!Subtarget->hasV6Ops() ||  in PerformORCombineToSMULWBT()
17623   if ((Subtarget->isThumb() || !Subtarget->hasV6Ops()) &&  in PerformMinMaxToSatCombine()
20020   if (!Subtarget->hasV6Ops())  in ExpandInlineAsm()
20948     if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {  in makeDMB()
21024     has64BitAtomicStore = Subtarget->hasV6Ops();  in shouldExpandAtomicStoreInIR()
21046     has64BitAtomicLoad = Subtarget->hasV6Ops();  in shouldExpandAtomicLoadInIR()
21067     hasAtomicRMW = Subtarget->hasV6Ops();  in shouldExpandAtomicRMWInIR()
21097     HasAtomicCmpXchg = Subtarget->hasV6Ops();  in shouldExpandAtomicCmpXchgInIR()