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Searched refs:hasStdExtZfh (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.h171 bool hasStdExtZfh() const { return HasStdExtZfh; } in hasStdExtZfh() function
H A DRISCVTargetTransformInfo.h253 if ((ScalarTy->isHalfTy() && ST->hasStdExtZfh()) ||
H A DRISCV.td76 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
81 : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZfhmin()">,
H A DRISCVISelLowering.cpp89 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
319 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
322 if (Subtarget.hasStdExtZfh()) { in RISCVTargetLowering()
922 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
957 if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZbb()) in RISCVTargetLowering()
1347 if (VT == MVT::f16 && !Subtarget.hasStdExtZfh()) in isFPImmLegal()
1357 return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) || in hasBitPreservingFPLogic()
11803 if (Subtarget.hasStdExtZfh() && VT == MVT::f16) in getRegForInlineAsmConstraint()
11916 if (Subtarget.hasStdExtZfh() && VT == MVT::f16) { in getRegForInlineAsmConstraint()
12219 return Subtarget.hasStdExtZfh(); in shouldConvertFpToSat()
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