89   if (Subtarget.hasStdExtZfh())  in RISCVTargetLowering()
319   if (Subtarget.hasStdExtZfh())  in RISCVTargetLowering()
322   if (Subtarget.hasStdExtZfh()) {  in RISCVTargetLowering()
922       if (Subtarget.hasStdExtZfh())  in RISCVTargetLowering()
957   if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZbb())  in RISCVTargetLowering()
1347   if (VT == MVT::f16 && !Subtarget.hasStdExtZfh())  in isFPImmLegal()
1357   return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) ||  in hasBitPreservingFPLogic()
1368   if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh())  in getRegisterTypeForCallingConv()
1380   if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh())  in getNumRegistersForCallingConv()
3129     if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) {  in LowerOperation()
7118     if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) {  in ReplaceNodeResults()
8522   if (Src.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfh())  in performFP_TO_INTCombine()
8569   if (Src.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfh())  in performFP_TO_INT_SATCombine()
11803       if (Subtarget.hasStdExtZfh() && VT == MVT::f16)  in getRegForInlineAsmConstraint()
11916       if (Subtarget.hasStdExtZfh() && VT == MVT::f16) {  in getRegForInlineAsmConstraint()
12219     return Subtarget.hasStdExtZfh();  in shouldConvertFpToSat()
12268     return Subtarget.hasStdExtZfh();  in isFMAFasterThanFMulAndFAdd()