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Searched refs:hasFullFP16 (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSubtarget.h348 bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); } in useFPVFMx16()
H A DARMTargetTransformInfo.cpp489 (EltVT == MVT::f16 && ST->hasFullFP16()); in getCastInstrCost()
1780 (ST->hasFullFP16() && LT.second == MVT::f16 && MTy == MVT::i32)) in getIntrinsicInstrCost()
1792 (ST->hasFullFP16() && LT.second == MVT::f16) || in getIntrinsicInstrCost()
1853 if (F->getReturnType()->isHalfTy() && !ST->hasFullFP16()) in isLoweredToCall()
1959 if (I.getType()->isHalfTy() && !ST->hasFullFP16()) in maybeLoweredToCall()
H A DARMPredicates.td114 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
H A DARMISelLowering.cpp786 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
798 if (!Subtarget->hasFullFP16()) in ARMTargetLowering()
842 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1074 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1418 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1428 if (Subtarget->hasFullFP16()) in ARMTargetLowering()
1516 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1549 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
2140 if (Subtarget->hasFullFP16()) { in MoveToHPR()
2153 if (Subtarget->hasFullFP16()) { in MoveFromHPR()
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H A DARMISelDAGToDAG.cpp3134 if (VT == MVT::v8i16 && Subtarget->hasFullFP16()) { in tryInsertVectorElt()
3154 if (VT == MVT::v8f16 && Subtarget->hasFullFP16()) { in tryInsertVectorElt()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp78 const bool HasFP16 = ST.hasFullFP16(); in AArch64LegalizerInfo()
222 !ST.hasFullFP16(); in AArch64LegalizerInfo()
229 return Query.Types[0] == s16 && !ST.hasFullFP16(); in AArch64LegalizerInfo()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp466 if (ST->hasFullFP16() && in getIntrinsicInstrCost()
475 (ST->hasFullFP16() && LT.second.getScalarType() == MVT::f16)) && in getIntrinsicInstrCost()
1868 if (ST->hasFullFP16()) in getCastInstrCost()
2152 (ST->hasFullFP16() && in getCmpSelInstrCost()
2619 if (LT.second.getScalarType() == MVT::f16 && !ST->hasFullFP16()) in getMinMaxReductionCost()
H A DAArch64ISelLowering.cpp585 if (Subtarget->hasFullFP16()) in AArch64TargetLowering()
602 if (!Subtarget->hasFullFP16()) { in AArch64TargetLowering()
690 if (Subtarget->hasFullFP16()) in AArch64TargetLowering()
699 if (Subtarget->hasFullFP16()) in AArch64TargetLowering()
989 if (Subtarget->hasFullFP16()) { in AArch64TargetLowering()
1110 if (Subtarget->hasFullFP16()) in AArch64TargetLowering()
3744 !Subtarget->hasFullFP16()) { in LowerVectorFP_TO_INT()
8796 else if (VT == MVT::f16 && Subtarget->hasFullFP16()) in isFPImmLegal()
12792 !Subtarget->hasFullFP16()) in shouldSinkOperands()
13611 return Subtarget->hasFullFP16(); in isFMAFasterThanFMulAndFAdd()
[all …]
H A DAArch64InstrInfo.td118 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp6014 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; in DecodeVCVTD() local
6032 if (hasFullFP16) { in DecodeVCVTD()
6073 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; in DecodeVCVTQ() local
6091 if (hasFullFP16) { in DecodeVCVTQ()