585   if (Subtarget->hasFullFP16())  in AArch64TargetLowering()
602   if (!Subtarget->hasFullFP16()) {  in AArch64TargetLowering()
690     if (Subtarget->hasFullFP16())  in AArch64TargetLowering()
699     if (Subtarget->hasFullFP16())  in AArch64TargetLowering()
989     if (Subtarget->hasFullFP16()) {  in AArch64TargetLowering()
1057       if (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()) {  in AArch64TargetLowering()
1110       if (Subtarget->hasFullFP16())  in AArch64TargetLowering()
1476       ((VT == MVT::v4f16 || VT == MVT::v8f16) && Subtarget->hasFullFP16()))  in addTypeForNEON()
1524       (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()))  in addTypeForNEON()
2870   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitStrictFPComparison()
2888   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitComparison()
2996   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitConditionalComparison()
3744       !Subtarget->hasFullFP16()) {  in LowerVectorFP_TO_INT()
3817   if (SrcVal.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {  in LowerFP_TO_INT()
3865       (!Subtarget->hasFullFP16() || DstElementWidth > 16)) {  in LowerVectorFP_TO_INT_SAT()
3925   if (SrcVT == MVT::f16 && !Subtarget->hasFullFP16()) {  in LowerFP_TO_INT_SAT()
3934        (SrcVT == MVT::f16 && Subtarget->hasFullFP16())) &&  in LowerFP_TO_INT_SAT()
4045   if (Op.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {  in LowerINT_TO_FP()
8102   if (LHS.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {  in LowerSELECT_CC()
8796   else if (VT == MVT::f16 && Subtarget->hasFullFP16())  in isFPImmLegal()
12109   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in LowerVSETCC()
12792           !Subtarget->hasFullFP16())  in shouldSinkOperands()
13611     return Subtarget->hasFullFP16();  in isFMAFasterThanFMulAndFAdd()
14479       (FloatBits != 16 || !Subtarget->hasFullFP16()))  in performFpToIntCombine()
15119   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in performExtractVectorEltCombine()
20035       (VT.getScalarType() == MVT::f16 && !Subtarget->hasFullFP16()))  in ReplaceAddWithADDP()
20789   if (FPVT == MVT::v8f16 && !Subtarget->hasFullFP16())  in shouldConvertFpToSat()