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Searched refs:hasExtraDefRegAllocReq (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/utils/TableGen/
H A DInstrDocsEmitter.cpp132 FLAG(hasExtraDefRegAllocReq) in EmitInstrDocs()
H A DCodeGenInstruction.h271 bool hasExtraDefRegAllocReq : 1; variable
H A DCodeGenInstruction.cpp415 hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq"); in CodeGenInstruction()
H A DInstrInfoEmitter.cpp1161 if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq) in emitRecord()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrDesc.h553 bool hasExtraDefRegAllocReq() const { in hasExtraDefRegAllocReq() function
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.cpp610 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
H A DAggressiveAntiDepBreaker.cpp379 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || in PrescanInstruction()
H A DMachineOperand.cpp128 return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle); in isRenamable()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstr64Bit.td354 let hasExtraDefRegAllocReq = 1 in
511 let hasExtraDefRegAllocReq = 1 in {
521 } // hasExtraDefRegAllocReq = 1
1502 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in {
1534 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1564 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
H A DPPCInstrInfo.td2617 let hasExtraDefRegAllocReq = 1 in {
2627 } // hasExtraDefRegAllocReq = 1
3081 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
3090 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
3098 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
3119 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
3128 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrThumb.td825 let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
837 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
870 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1,
1740 hasExtraDefRegAllocReq = 1 in
H A DARMInstrInfo.td2837 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2962 let hasExtraDefRegAllocReq = 1 in {
2990 } // hasExtraDefRegAllocReq = 1
3536 let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
3550 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3557 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
5235 let hasExtraDefRegAllocReq = 1 in
5250 let hasExtraDefRegAllocReq = 1 in
H A DARMInstrThumb2.td1454 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1461 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
2038 let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
3633 let hasExtraDefRegAllocReq = 1 in
3667 let hasExtraDefRegAllocReq = 1 in
3853 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
H A DARMInstrNEON.td596 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
999 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1113 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1367 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1418 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1659 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
H A DARMInstrVFP.td301 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineInstr.h1140 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td378 let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$rs = $wb" in {
473 hasExtraDefRegAllocReq = 1,
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td866 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td566 bit hasExtraDefRegAllocReq = false; // Defs have special regalloc requirement?
1633 // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1
/llvm-project-15.0.7/llvm/docs/TableGen/
H A DProgRef.rst1935 bit hasExtraDefRegAllocReq = 0;