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/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Dhfsplat.ll19 %7 = phi half* [ %0, %4 ], [ %11, %20 ]
25 %11 = getelementptr half, half* %0, i32 %10
30 %14 = getelementptr half, half* %0, i32 %13
31 %15 = bitcast half* %14 to <64 x half>*
32 …half> <half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0x…
33 %16 = getelementptr half, half* %14, i32 64
34 %17 = bitcast half* %16 to <64 x half>*
35 …half> <half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0x…
48 %24 = phi half* [ %28, %23 ], [ %7, %6 ]
50 store half 0xH4170, half* %24, align 2
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dpacked-math.ll45 %i1 = load half, half* %b, align 2
52 store half %mul, half* %c, align 2
69 %i0 = load half, half* %a, align 2
70 %i1 = load half, half* %b, align 2
99 %fma0 = call half @llvm.fma.f16(half %i0, half %i1, half %i2)
106 %fma1 = call half @llvm.fma.f16(half %i3, half %i4, half %i5)
174 %fma0 = call half @llvm.fma.f16(half %i0.fabs, half %i1, half %i2)
183 %fma1 = call half @llvm.fma.f16(half %i3.fabs, half %i4, half %i5)
212 %fma0 = call half @llvm.fma.f16(half %i0, half %i1.fabs, half %i2)
219 %fma1 = call half @llvm.fma.f16(half %i3, half %i4, half %i5)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfp16-vector-load-store.ll217 ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %0
271 ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %0
333 ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %0
360 ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %0
367 … <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4lane.v4f16.p0f16(<4 x half…
373 … <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4lane.v8f16.p0f16(<8 x half…
388 define { <4 x half>, <4 x half>, <4 x half> } @load_lane_64_3(half* %a, <4 x half> %b, <4 x half> %…
397 define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @load_lane_64_4(half* %a, <4 x half> %b, …
402 ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %0
442 define { <8 x half>, <8 x half>, <8 x half> } @load_lane_128_3(half* %a, <8 x half> %b, <8 x half> …
[all …]
H A Dfp16_intrinsic_lane.ll4 declare half @llvm.aarch64.neon.fmulx.f16(half, half)
7 declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)
8 declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
9 declare half @llvm.fma.f16(half, half, half) #1
91 %0 = tail call half @llvm.fma.f16(half %b, half %extract, half %a)
113 %sub = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
126 …%sub = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half…
138 %sub = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
150 …%sub = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half…
163 %sub = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
[all …]
H A Dfp16_intrinsic_scalar_3op.ll3 define dso_local half @t_vfmah_f16(half %a, half %b, half %c) {
8 %0 = tail call half @llvm.fma.f16(half %b, half %c, half %a)
12 define half @fnma16(half %a, half %b, half %c) nounwind readnone ssp {
16 %0 = tail call half @llvm.fma.f16(half %a, half %b, half %c)
26 %0 = tail call half @llvm.fma.f16(half %a, half %mul, half %c)
36 %0 = tail call half @llvm.fma.f16(half %mul, half %a, half %c)
50 define half @test_fmsub(half %a, half %b, half %c) {
60 define half @test_fnmadd(half %a, half %b, half %c) {
71 define half @test_fmadd(half %a, half %b, half %c) {
82 define half @test_fnmsub(half %a, half %b, half %c) {
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Davx512fp16-fma-intrinsics.ll13 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
30 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
42 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
43 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
60 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
61 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
323 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
398 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
399 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
420 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
[all …]
H A Davx512fp16vl-fma-intrinsics.ll11 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
28 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
40 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
41 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
58 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
59 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
140 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
197 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
198 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
219 …half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000…
[all …]
H A Dbuild_fp16_constant_vector.ll5 define dso_local <32 x half> @foo(<32 x half> %a, <32 x half> %b, <32 x half> %c) {
15 …half> @llvm.fma.v32f16(<32 x half> %a, <32 x half> <half 0xH3C00, half 0xH3C00, half 0xH3C00, half…
16 …half> @llvm.fma.v32f16(<32 x half> %b, <32 x half> <half 0xH3C00, half 0xH3C00, half 0xH3C00, half…
17 %2 = fadd <32 x half> %0, %1
18 ret <32 x half> %2
21 declare <32 x half> @llvm.fma.v32f16(<32 x half>, <32 x half>, <32 x half>)
H A Davx512fp16-fma-commute.ll4 declare half @llvm.fma.f16(half, half, half)
5 declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
9 define half @fma_123_f16(half %x, half %y, half %z) {
14 %a = call half @llvm.fma.f16(half %x, half %y, half %z)
18 define half @fma_213_f16(half %x, half %y, half %z) {
23 %a = call half @llvm.fma.f16(half %y, half %x, half %z)
27 define half @fma_231_f16(half %x, half %y, half %z) {
32 %a = call half @llvm.fma.f16(half %y, half %z, half %x)
36 define half @fma_321_f16(half %x, half %y, half %z) {
45 define half @fma_132_f16(half %x, half %y, half %z) {
[all …]
H A Davx512fp16-arith.ll28 …half> %a, <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.…
37 …half> %a, <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.…
46 …%b = fadd <8 x half> %a, <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, ha…
297 define half @fneg(half %x) {
317 define half @fabs(half %x) {
328 define half @fcopysign(half %x, half %y) {
334 %a = call half @llvm.copysign.f16(half %x, half %y)
337 declare half @llvm.copysign.f16(half, half)
355 …%a = fsub <8 x half> <half -0.0, half -0.0, half -0.0, half -0.0, half -0.0, half -0.0, half -0.0,…
396 …half> <half -0.0, half -0.0, half -0.0, half -0.0, half -0.0, half -0.0, half -0.0, half -0.0, hal…
[all …]
H A Dstack-folding-fp-avx512fp16-fma.ll18 declare <32 x half> @llvm.fma.v32f16(<32 x half>, <32 x half>, <32 x half>)
811 declare half @llvm.fma.f16(half, half, half)
858 %3 = call half @llvm.fma.f16(half %a0, half %a1, half %2)
867 %3 = call half @llvm.fma.f16(half %a1, half %a0, half %2)
876 %3 = call half @llvm.fma.f16(half %a1, half %a2, half %2)
967 %4 = call half @llvm.fma.f16(half %2, half %a1, half %3)
977 %4 = call half @llvm.fma.f16(half %2, half %a0, half %3)
987 %4 = call half @llvm.fma.f16(half %2, half %a2, half %3)
997 %4 = call half @llvm.fma.f16(half %2, half %a1, half %3)
1007 %4 = call half @llvm.fma.f16(half %2, half %a2, half %3)
[all …]
H A Davx512fp16-rndscale.ll4 declare <8 x half> @llvm.ceil.v8f16(<8 x half>)
5 declare <16 x half> @llvm.ceil.v16f16(<16 x half>)
6 declare <32 x half> @llvm.ceil.v32f16(<32 x half>)
8 define <8 x half> @ceil_v8f16(<8 x half> %p) {
13 %t = call <8 x half> @llvm.ceil.v8f16(<8 x half> %p)
17 define <16 x half> @ceil_v16f16(<16 x half> %p) {
26 define <32 x half> @ceil_v32f16(<32 x half> %p) {
35 declare <8 x half> @llvm.floor.v8f16(<8 x half>)
39 define <8 x half> @floor_v8f16(<8 x half> %p) {
66 declare <8 x half> @llvm.trunc.v8f16(<8 x half>)
[all …]
H A Dstack-folding-fp-avx512fp16vl-fma.ll11 define <8 x half> @stack_fold_fmadd123ph(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2) {
15 %2 = call <8 x half> @llvm.fma.v8f16(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2)
18 declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
20 define <8 x half> @stack_fold_fmadd213ph(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2) {
24 %2 = call <8 x half> @llvm.fma.v8f16(<8 x half> %a1, <8 x half> %a0, <8 x half> %a2)
28 define <8 x half> @stack_fold_fmadd231ph(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2) {
32 %2 = call <8 x half> @llvm.fma.v8f16(<8 x half> %a1, <8 x half> %a2, <8 x half> %a0)
36 define <8 x half> @stack_fold_fmadd321ph(<8 x half> %a0, <8 x half> %a1, <8 x half> %a2) {
40 %2 = call <8 x half> @llvm.fma.v8f16(<8 x half> %a2, <8 x half> %a1, <8 x half> %a0)
48 %2 = call <8 x half> @llvm.fma.v8f16(<8 x half> %a0, <8 x half> %a2, <8 x half> %a1)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/
H A D4x2xhalf.ll4 %in1b = bitcast half* %rd0 to <2 x half>*
5 %load1 = load <2 x half>, <2 x half>* %in1b, align 4
8 store <2 x half> %s1, <2 x half>* %in1b, align 4
9 %in2 = getelementptr half, half* %rd0, i64 2
10 %in2b = bitcast half* %in2 to <2 x half>*
15 %in3 = getelementptr half, half* %rd0, i64 4
16 %in3b = bitcast half* %in3 to <2 x half>*
21 %in4 = getelementptr half, half* %rd0, i64 6
22 %in4b = bitcast half* %in4 to <2 x half>*
39 %in1b = bitcast half* %rd0 to <3 x half>*
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dmath-intrins-sm53-ptx42.ll4 declare half @llvm.nvvm.fma.rn.f16(half, half, half)
5 declare half @llvm.nvvm.fma.rn.ftz.f16(half, half, half)
6 declare half @llvm.nvvm.fma.rn.sat.f16(half, half, half)
7 declare half @llvm.nvvm.fma.rn.ftz.sat.f16(half, half, half)
8 declare <2 x half> @llvm.nvvm.fma.rn.f16x2(<2 x half>, <2 x half>, <2 x half>)
14 define half @fma_rn_f16(half %0, half %1, half %2) {
17 %res = call half @llvm.nvvm.fma.rn.f16(half %0, half %1, half %2)
22 define half @fma_rn_ftz_f16(half %0, half %1, half %2) {
25 %res = call half @llvm.nvvm.fma.rn.ftz.f16(half %0, half %1, half %2)
30 define half @fma_rn_sat_f16(half %0, half %1, half %2) {
[all …]
H A Dmath-intrins-sm80-ptx70-instcombine.ll5 declare half @llvm.nvvm.fmin.f16(half, half)
6 declare half @llvm.nvvm.fmin.ftz.f16(half, half)
11 declare half @llvm.nvvm.fmin.nan.f16(half, half)
12 declare half @llvm.nvvm.fmin.ftz.nan.f16(half, half)
16 declare half @llvm.nvvm.fmax.f16(half, half)
17 declare half @llvm.nvvm.fmax.ftz.f16(half, half)
28 declare half @llvm.nvvm.fma.rn.f16(half, half, half)
29 declare half @llvm.nvvm.fma.rn.ftz.f16(half, half, half)
34 define half @fmin_f16(half %0, half %1) {
274 define half @fma_rn_f16(half %0, half %1, half %2) {
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.fmad.ftz.f16.ll5 declare half @llvm.amdgcn.fmad.ftz.f16(half %a, half %b, half %c)
14 %a.val = load half, half addrspace(1)* %a
17 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %b.val, half %c.val)
18 store half %r.val, half addrspace(1)* %r
30 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half 8.0, half %b.val, half %c.val)
43 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half 8.0, half %c.val)
56 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %b.val, half 8.0)
73 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %neg.b, half %c.val)
90 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %abs.b, half %c.val)
108 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %neg.abs.b, half %c.val)
[all …]
H A Dpacked-op-sel.ll253 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2
280 %vec2.fneg = fsub <2 x half> <half -0.0, half -0.0>, %vec2
389 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2
446 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2
475 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2
503 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2
531 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2
559 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2
642 %fadd = fadd <2 x half> %vec2, <half 2.0, half 2.0>
680 %fadd = fadd <2 x half> %vec2, <half 2.0, half 2.0>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfp16-vminmaxnm-vector.ll8 define <4 x half> @test1(<4 x half> %A, <4 x half> %B) {
17 define <4 x half> @test2(<4 x half> %A, <4 x half> %B) {
26 define <4 x half> @test3(<4 x half> %A, <4 x half> %B) {
35 define <4 x half> @test4(<4 x half> %A, <4 x half> %B) {
44 define <4 x half> @test5(<4 x half> %A, <4 x half> %B) {
53 define <4 x half> @test6(<4 x half> %A, <4 x half> %B) {
62 define <4 x half> @test7(<4 x half> %A, <4 x half> %B) {
71 define <4 x half> @test8(<4 x half> %A, <4 x half> %B) {
82 define <4 x half> @test11(<4 x half> %A, <4 x half> %B) {
91 define <4 x half> @test12(<4 x half> %A, <4 x half> %B) {
[all …]
H A Dfp16-load-store.ll3 define void @load_zero(half* %in, half* %out) {
8 %load = load half, half* %arrayidx, align 2
9 store half %load, half* %out
19 store half %load, half* %out
30 store half %load, half* %out
40 store half %load, half* %out
51 store half %load, half* %out
61 store half %load, half* %arrayidx
71 store half %load, half* %arrayidx
82 store half %load, half* %arrayidx
[all …]
H A Dfp16-fullfp16.ll14 store half %r, half* %p
28 store half %r, half* %p
42 store half %r, half* %p
56 store half %r, half* %p
76 store half %r, half* %p
86 store half %a, half* %q
400 %v = call half @llvm.fma.f16(half %a, half %b, half %c)
582 %v = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
591 declare half @llvm.pow.f16(half %a, half %b)
597 declare half @llvm.fma.f16(half %a, half %b, half %c)
[all …]
H A Dvsel-fp16.ll17 %a = load volatile half, half* %a_ptr
21 store half %val1, half* @varhalf
40 store half %val1, half* @varhalf
59 store half %val1, half* @varhalf
101 define void @test_vsel32ogt(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
125 define void @test_vsel32oge(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
149 define void @test_vsel32oeq(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
173 define void @test_vsel32ugt(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
197 define void @test_vsel32uge(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
221 define void @test_vsel32olt(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
[all …]
H A Darmv8.2a-fp16-vector-intrinsics.ll336 %sub.i = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %a
345 …%sub.i = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, ha…
966 %sub.i = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
977 …%sub.i = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, ha…
1326 …lare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4lane.v8f16.p0i8(i8*, <8…
1353 define { <8 x half>, <8 x half>, <8 x half> } @test_vld3q_lane_f16(i8*, <8 x half>, <8 x half>, <8 …
1362 define { <4 x half>, <4 x half>, <4 x half> } @test_vld3_lane_f16(i8*, <4 x half>, <4 x half>, <4 x…
1370 define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @test_vld4lane_v8f16_p0i8(i8*, <8 x half>…
1376 ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %5
1378 define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @test_vld4lane_v4f16_p0i8(i8*, <4 x half>…
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/
H A Dinterleaved-load-half.ll30 %0 = load half, half* %arrayidx, align 4
33 %1 = load half, half* %arrayidx2, align 4
35 store half %add3, half* %arrayidx2, align 4
38 %2 = load half, half* %arrayidx5, align 4
41 %3 = load half, half* %arrayidx8, align 4
43 store half %add9, half* %arrayidx8, align 4
46 %4 = load half, half* %arrayidx11, align 4
49 %5 = load half, half* %arrayidx14, align 4
54 %6 = load half, half* %arrayidx17, align 4
57 %7 = load half, half* %arrayidx20, align 4
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/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dhalf-arith-strict.ll10 define half @fadd_h(half %a, half %b) nounwind strictfp {
20 define half @fsub_h(half %a, half %b) nounwind strictfp {
30 define half @fmul_h(half %a, half %b) nounwind strictfp {
40 define half @fdiv_h(half %a, half %b) nounwind strictfp {
62 ;define half @fmin_h(half %a, half %b) nounwind strictfp {
74 define half @fmadd_h(half %a, half %b, half %c) nounwind strictfp {
84 define half @fmsub_h(half %a, half %b, half %c) nounwind strictfp {
97 define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp {
113 define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp {
129 define half @fnmsub_h(half %a, half %b, half %c) nounwind strictfp {
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